View MEGA48MEGA88MEGA168_286453.PDF datasheet online --- IC-ON-LINE

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* 8 AVR(R) * RISC
- 131 - - 32 x 8 - - 16 MHz 16 MIPS - - 4/8/16K Flash (ATmega48/88/168) : 10,000 - Boot Boot - 256/512/512 EEPROM (ATmega48/88/168) : 100,000 - 512/1K/1K SRAM (ATmega48/88/168) - - 8 / - 16 / - RTC - PWM - 8 10 ADC(TQFP MLF ) - 6 10 ADC( PDIP ) - USART - / SPI - - - - MCU - - RC - / - ADC Standby I/O - 23 I/O - 32 TQFP 32 MLF : - ATmega48V/88V/168V1.8 - 5.5V - ATmega48/88/1682.7 - 5.5V : - -40C 85C : - ATmega48V/88V/168V: 0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.4 - 5.5V - ATmega48/88/168: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V - 1 MHz, 1.8V: 300A 32 kHz, 1.8V: 20A ( ) - : 1.8V 0.5A
*
*
8K Flash 8 ATmega48/V ATmega88/V ATmega168/V
*
* * * * *

Rev. 2545A-AVR-09/03
1
Figure 1. ATmega48/88/168
PDIP
(PCINT14/RESET) PC6 (PCINT16/RXD) PD0 (PCINT17/TXD) PD1 (PCINT18/INT0) PD2 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND AREF AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/OC2A/PCINT3) PB2 (SS/OC1B/PCINT2) PB1 (OC1A/PCINT1)
TQFP Top View
PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10)
MLF Top View
PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
(PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5)
(PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4
NOTE: Bottom pad should be soldered to ground.
2
ATmega48/88/168
2545A-AVR-09/03
(PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4
ATmega48/88/168
ATmega48/88/168 AVRRISC 8 CMOS ATmega48/88/168 1 MIPS/MHz Figure 2.
GND VCC
Watchdog Timer Watchdog Oscillator
Power Supervision POR / BOD & RESET
debugWIRE
PROGRAM LOGIC
Oscillator Circuits / Clock Generation
Flash
SRAM
CPU EEPROM
AVCC AREF GND
8bit T/C 0
16bit T/C 1
A/D Conv.
2
DATABUS
8bit T/C 2
Analog Comp.
Internal Bandgap
6
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
RESET XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
3
2545A-AVR-09/03
AVR 32 (ALU) CISC 10 ATmega48/88/168: 4K/8K/16KFlash( RWW) 256/512/512 EEPROM 512/1K/1K SRAM 23 I/O 32 / (T/C), / USART SPI 6 10 ADC (TQFP MLF 8 10 ADC) CPU SRAM T/C USART SPI ADC CPU I/O ADC ADC Standby ATmega48/88/168 Atmel ISP Flash SPI Flash Flash FLASH RWW 8 RISC CPU Flash ATmega48/88/168 ATmega48/88/168 AVR C /
ATmega48,ATmega88, ATmega168
ATmega48ATmega88 ATmega168 boot loader Table1 Table 1.
ATmega48 ATmega88 ATmega168 Flash 4K 8K 16K EEPROM 256 512 512 RAM 512 1K 1K (16 ) (16 ) (32 )
ATmega88 ATmega168 Boot Loader SPM FLASH ATmega48 Boot Loader SPM Flash

VCC GND B (PB7..0) XTAL1/ XTAL2/TOSC1/TOSC2
AVR
B 8 I/O B
4
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
PB6 PB7 RC ASSR AS2 PB7..6 / 2 TOSC2..1 B P66" B " P23" " C (PC5..0) C 7 I/O C RSTDISBL PC6I/O PC6C RSTDISBLPC6Reset P37Table20 C P69" C " D (PD7..0) D 8 I/O D D P72" D " AVCC AVCC A/D PC3..0 PC7..6 ADC AVCC VCC ADC VCC PC6..4 VCC AREF ADC TQFP MLF ADC7..6 10 A/D AVCC C C
PC6/RESET
AREF ADC7..6 (TQFP MLF )
5
2545A-AVR-09/03
AVR CPU

AVR CPU Figure 3. AVR
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) FLASH 32 8 ALU ALU 6 3 16 16 X Y Z 6
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ALU ALU / 16 16 32 / SPM (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F ATmega48/88/168 SRAM 0x60 - 0xFF I/O ST/STS/STD LD/LDS/LDD
ALU--
AVR ALU 32 ALU ALU 3 / " "
7
2545A-AVR-09/03
ALU AVR SREG
/ 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* 7 - I: I I RETI I SEI CLI * 6 - T: BLD BST T BST T BLD T * 5 - H: H BCD " " * 4 - S: S = N
V
S N 2 V * 3 - V: 2 2 * 2 - N: * 1 - Z: * 0 - C:
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 4 CPU 32
8
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 4. AVR CPU
7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X X Y Y Z Z 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Figure 4 32 SRAM X Y Z
9
2545A-AVR-09/03
XYZ
R26..R31 Figure 5 Figure 5. X Y Z
15 X 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15 Y 7 R29 (0x1D) 15 Z 7 R31 (0x1F)
YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E)
YL
0 0
ZL 0
0

/ AVR SRAM 0xFF PUSH POP RET RETI AVRI/O8 AVR SPL SPH
15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
10
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / Figure 6.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure7 ALU Figure 7. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I PC (Boot) BLB02 BLB12 P255" " P48" " RESET INT0 - 0 MCU MCUCR IVSEL ( P48" " ), Flash BOOTRSTFlash P241"Boot Loader RWW ATmega88 ATmega168" I I RETI I 11
2545A-AVR-09/03
"1" "0" I AVR CLI CLI CLI EEPROM EEPROM
in cli r16, SREG ; ; EEPROM ; SREG (I ) ; SREG
sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16
C
char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1<12
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
SEI
sei ; sleep ; ; : MCU ;
C
_SEI(); /* */ _SLEEP(); /* */ /* : MCU */
AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I
13
2545A-AVR-09/03
ATmega48/88/168
ATmega48/88/168 AVR ATmega48/88/168 EEPROM
Flash ATmega48/88/168 4/8/16K Flash AVR 16 32 Flash 2/4/8K x 16. ATmega88
ATmega168 Flash (Boot) ATmega48 SPM Flash P236" (SPM) - SPMCSR" P244 SPMEN
Flash 10,000 ATmega48/88/168 (PC) 11/12/13 2/4/8K P234"FlashATmega48" P241"Boot LoaderRWW ATmega88 ATmega168" P255"" SPIJTAGFlash ( LPM ) P11" " Figure 8. ATmega48
Program Memory 0x0000
Application Flash Section
0x7FF
14
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 9. ATmega88 ATmega168
Program Memory 0x0000
Application Flash Section
Boot Flash Section 0x0FFF/0x1FFF
SRAM
Figure10 ATmega48/88/168 SRAM ATmega48/88/168 64 I/O( IN/OUT ) I/O 0x60 - 0xFF ST/STS/STD LD/LDS/LDD 768/1280/1280 I/O I/O SRAM 32 64 I/O 160 I/O 512/1024/1024 SRAM 5 R26 R31 Y Z 63 X Y Z ATmega48/88/168 32 64 I/O 160 I/O 512/1024/1024 SRAM P8" "
15
2545A-AVR-09/03
Figure 10.
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (512/1024/1024 x 8) 0x02FF/0x04FF/0x04FF
Figure11 SRAM clkCPU Figure 11. SRAM
T1 T2 T3
0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF 0x0100
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
EEPROM
ATmega48/88/168 256/512/512 EEPROM EEPROM 100,000 EEPROM SPI EEPROM P255" "
EEPROM /
EEPROM I/O EEPROM Table3 EEPROM / VCC / CPU P21" EEPROM " EEPROM EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2
16
ATmega48/88/168
2545A-AVR-09/03
Read
Write
ATmega48/88/168
EEPROM --EEARH EEARL
15 - EEAR7 7 / R R/W 0 X 14 - EEAR6 6 R R/W 0 X 13 - EEAR5 5 R R/W 0 X 12 - EEAR4 4 R R/W 0 X 11 - EEAR3 3 R R/W 0 X 10 - EEAR2 2 R R/W 0 X 9 - EEAR1 1 R R/W 0 X 8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
* 15..9 - Res: * 8..0 - EEAR8..0: EEPROM EEPROM - EEARH EEARL 256/512/512 EEPROM EEPROM 0 255/511/511 EEAR EEPROM EEAR8 ATmega48 "0" EEPROM --EEDR
/ 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR
* 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM --EECR
/ 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR
* 7..4 - Res: * 5, 4 - EEPM1 EEPM0: EEPROM EEPROM EEPE EEPROM ( ) Table2 EEPE EEPMn EEPROM EEPMn 0b00
17
2545A-AVR-09/03
Table 2. EEPROM
EEPM1 0 0 1 1 EEPM0 0 1 0 1 3.4 ms 1.8 ms 1.8 ms - ( )
* 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * 2 - EEMWE: EEPROM EEMWEEEWE"1"EEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 EEPROM EEPE * 1 - EEPE: EEPROM EEPE EEPROM EEPROM EEPE EEPROM EEMPE EEPROM ( 3 4 ) 1. EEPE "0" 2. SPMCSR SPMEN 3. EEPROM EEAR ( ) 4. EEPROM EEDR ( ) 5. EECR EEMPE "1" EEPE 6. EEMPE 4 EEPE CPU Flash EEPROM EEPROM Flash CPU Flash CPU Flash P241"Boot Loader RWW ATmega88 ATmega168" : 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEPE EEPE CPU * 0 - EERE: EEPROM EERE EEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEPE EEPROM EEAR
18
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
EEPROM Table3 CPU EEPROM Table 3. EEPROM
CPU EEPROM RC 26,368 3.3 ms
C EEPROM EEPROM SPM
EEPROM_write: ; sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; (r16) ; EEMWE ; EEWE
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1<19
2545A-AVR-09/03
C EEPROM
EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; EERE ;
C
unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM
CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
ATmega48/88/168 I/O P311" " ATmega48/88/168 I/O I/O I/O LD/LDS/LDDST/STS/STD 32I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20 ATmega48/88/168 64 I/O( IN/OUT ) I/O 0x60 - 0xFF ST/STS/STD LD/LDS/LDD
20
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
"0" I/O "1" CBI SBI I/O "1" CBI SBI 0x00 to 0x1F I/O I/O ATmega48/88/1683I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC
/ 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR2
I/O 2--GPIOR2
I/O 1--GPIOR1
/
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR1
I/O 0--GPIOR0
/
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR0
21
2545A-AVR-09/03
Figure12 AVR P32" " Figure 12.
Asynchronous Timer/Counter General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
AVR Clock Control Unit
System Clock Prescaler
Reset Logic
Watchdog Timer
Source clock Clock Multiplexer
Watchdog clock Watchdog Oscillator
Timer/Counter Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated RC Oscillator
CPU --clkCPU I/O --clkI/O
CPUAVR CPU I/O I/O / SPI USART I/O I/O USI clkI/O Flash Flash CPU / 32 kHz / ADC ADCCPUI/O ADC
Flash --clkFLASH --clkASY ADC --clkADC
22
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Flash AVR Table 4. (1)
128 kHz RC RC Note: 1. "1" "0" CKSEL3..0 1111 - 1000 0111 - 0110 0101 - 0100 0011 0010 0000 0001
RC 8.0MHz CKDIV8 1.0MHz (CKSEL = "0010" SUT = "10" CKDIV8 = "0") Vcc Vcc (tTOUT) P37"" (tTOUT) SUTx CKSELx Table5 P283"ATmega48/88/168 - " Table 5.
(VCC = 5.0V) 0 ms 4.1 ms 65 ms (VCC = 3.0V) 0 ms 4.3 ms 69 ms 0 4K (4,096) 8K (8,192)
Vcc AVR MCU Vcc / BOD BOD Vcc BOD BOD 6 32K CPU Vcc
23
2545A-AVR-09/03
XTAL1 XTAL2 Figure13 XTAL2 P26" " C1 C2 Table6 Figure 13.
C2 C1
XTAL2 XTAL1 GND
CKSEL3..1 Table6 Table 6. (3)
(1) (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 Notes: CKSEL3..1 100(2) 101 110 111 C1 C2 (pF) - 12 - 22 12 - 22 12 - 22
1. 2. 3. 8 MHz (VCC )CKDIV8 8
Table7 CKSEL0 SUT1..0
24
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 7.
258 CK 258 CK 1K CK 1K CK 1K CK 16K CK 16K CK 16K CK (VCC = 5.0V) 14CK + 4.1 ms
(1)
/ BOD BOD Notes:
CKSEL0 0 0 0 0 1 1 1 1
SUT1..0 00 01 10 11 00 01 10 11
14CK + 65 ms(1) 14CK(2) 14CK + 4.1 ms(2) 14CK + 65 ms(2) 14CK 14CK + 4.1 ms 14CK + 65 ms
1. 2.
XTAL1 XTAL2 Figure13 XTAL2 P25" " Vcc = 2.7 - 5.5V C1 C2 Table9 CKSEL3..1 Table8 Table 8. (2)
(1) (MHz) 0.4 - 25 Notes: CKSEL3..1 111 C1 C2 (pF) 12 - 22
1. 2. 8 MHz (VCC )CKDIV8 8
25
2545A-AVR-09/03
Figure 14.
C2 C1
XTAL2 XTAL1 GND
Table 9.
258 CK 258 CK 1K CK 1K CK 1K CK 16K CK 16K CK 16K CK (VCC = 5.0V) 14CK + 4.1 ms
(1)
/ BOD BOD Notes:
CKSEL0 0 0 0 0 1
SUT1..0 00 01 10 11 00 01 10 11
14CK + 65 ms(1) 14CK(2) 14CK + 4.1 ms(2) 14CK + 65 ms(2) 14CK 14CK + 4.1 ms 14CK + 65 ms
1 1 1
1. 2.
26
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
32.768 kHz Figure13 Table10 SUT CKSEL0 Table 10.
1K CK 1K CK 1K CK BOD 32K CK 32K CK 32K CK Note: 14CK 14CK + 4.1 ms 14CK + 65 ms (VCC = 5.0V) 14CK
(1)
BOD
CKSEL0 0 0 0 0 1 1 1 1
SUT1..0 00 01 10 11 00 01 10 11
14CK + 4.1 ms(1) 14CK + 65 ms
(1)
1.
RC
RC 8.0 MHz , 3V25C CKDIV8 P31" " Table11 CKSEL OSCCAL RC 3V25C 1% OSCCAL 7.3 - 8.1 MHz 1% P259" " Table 11. RC (1)(3)
(2) (MHz) 7.3 - 8.1 Notes: CKSEL3..0 0010
1. 2. 3. 8 MHz (VCC )CKDIV8 8
SUT P28Table12
27
2545A-AVR-09/03
Table 12. RC
BOD 6 CK 6 CK 6 CK Note: (VCC = 5.0V) 14CK
(1)
SUT1..0 00 01 10 11
14CK + 4.1 ms 14CK + 65 ms(2)
1. RSTDISBL 14CK + 4.1 ms 2.
--OSCCAL
/
7 CAL7 R/W
6 CAL6 R/W
5 CAL5 R/W
4 CAL4 R/W
3 CAL3 R/W
2 CAL2 R/W
1 CAL1 R/W
0 CAL0 R/W OSCCAL
* 7..0 - CAL7..0: 25C 8.0 MHz 7.3 - 8.1 MHz 1% EEPROM Flash EEPROM Flash 8.8 MHz EEPROM Flash CAL7 0 1 OSCCAL = 0x7F OSCCAL = 0x80 CAL6..0 0x00 0x7F 7.3 - 8.1 MHz CAL6..0 1 2%
128 kHz
128 kHz 3V 25C128 kHz CKSEL "11" Table13 Table 13. 128 kHz
128 kHz Note: 1. CKSEL3..0 0011
28
ATmega48/88/168
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ATmega48/88/168
SUT Table14 Table 14. 128 kHz
BOD 6 CK 6 CK 6 CK Note: 14CK
(1)
SUT1..0 00 01 10 11
14CK + 4 ms 14CK + 64 ms
1. RSTDISBL 14CK + 4.1 ms
Figure15 CKSEL Table15 Table 15. (2)
(1) (MHz) 0 - 100 Notes: CKSEL3..0 0000 C1 C2 (pF) 12 - 22
1. 2. 8 MHz (VCC )CKDIV8 8
Figure 15.
NC
XTAL2
EXTERNAL CLOCK SIGNAL
XTAL1
GND
SUT Table16 Table 16.
BOD 6 CK 6 CK 6 CK (VCC = 5.0V) 14CK 14CK + 4.1 ms 14CK + 65 ms SUT1..0 00 01 10 11
MCU 2% MCU
29
2545A-AVR-09/03
P31" "
CKOUT CLKO CKOUT I/O CLKO RC 32.768 kHz / 2 / TOSC1/TOSC2 XTAL1 /XTAL2 RC / P24Figure 13 ASSR EXTCLK "1" TOSC1 32 kHz P139" / "
/
ATmega48/88/168 CLKPR CPU clkI/O clkADC clkCPU clkFLASH Table17
/ 7
CLKPCE
--CLKPR
6
-
5
-
4
-
3
CLKPS3
2
CLKPS2
1
CLKPS1
0
CLKPS0 CLKPR
R/W 0
R 0
R 0
R 0
R/W
R/W
R/W
R/W
* 7 - CLKPCE: CLKPS CLKPCE "1" CLKPR "0" CLKPCE CLKPCE "1" 4 CLKPS 4 CLKPCE 4 CLKPCE CLKPCE * 3..0 - CLKPS3..0: 3 - 0 MCU Table17 CLKPS 1. (CLKPCE) CLKPR 2. 4 CLKPS CLKPCE CKDIV8 CLKPS CKDIV8 CLKPS "0000" CKDIV8 CLKPS"0011" 8 CKDIV8 CLKPS
30
ATmega48/88/168
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ATmega48/88/168
CKDIV8 Table 17.
CLKPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 256
31
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MCU AVR 5 SMCR SE SLEEP ( ADC Standby ) SMCR SM2SM1 SM0 Table18 MCU 4 ( MCU ) MCU MCU SLEEP MCU SRAM MCU P22Figure 12 ATmega48/88/168
--SMCR
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 SM2 R/W 0 2 SM1 R/W 0 1 SM0 R/W 0 0 SE R/W 0 SMCR
* 7..4 Res: ATmega48/88/168 "0" * 3 2 1 - SM2..0: 2 1 0 Table18 Table 18.
SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 ADC Standby(1)
1. Standby
* 0 - SE: MCU SLEEP SE SLEEP SE SE
32
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
SM2..0 000 SLEEP MCU CPU SPIUSARTADC / clkCPU clkFLASH USART MCU MCU ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU ADC / 2 ( ) clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD / 2 SPM/EEPROM INT0 INT1 MCU ADC
SM2..0 010 SLEEP MCU ( ) BOD INT0 INT1 MCU MCU P76" " MCU CKSEL P24""
SM2..0011 SLEEPMCU / 2 / / 2 MCU TIMSK2 SREG I / 2 / 2 / 2 / / 2 / 2
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2545A-AVR-09/03
Standby
SM2..0 110 SLEEP MCUStandby 6 Table 19. MCU
INT1, INT0 Pin TWI SPM/ EEPROM
2
clkFLASH
clkADC
clkCPU
clkASY
ADC X X
clkIO
ADC Standby Notes:
(1)
X
X X
X X
X X
X(2) X(2)
X X(3) X
(3)
X X X X X
X X(2)
X X
X
X X
X
X(3) X(3)
X
1. 2. / 2 3. INT1 INT0
AVR ADC ADC P217" " ADC P214" " BOD BODLEVEL BOD P40" " BOD BOD ADC P43" " P44" " I/O clkI/O ADC clkADC

BOD
34
ATmega48/88/168
2545A-AVR-09/03
I/O
ATmega48/88/168
P63" " VCC/2 VCC/2 (DIDR1 DIDR0) P216" 1 - DIDR1" P231" 0 - DIDR0" DWEN
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2545A-AVR-09/03
AVR I / O ATmega168 JMP ATmega48 ATmega88 RJMP Boot -- -- ( ATmega88/168) Figure16 Table20 I/O MCU SUT CKSEL P24" " ATmega48/88/168 4 * * * * VPOT MCU RESET MCU (BOD) VBOT MCU
Figure 16.
DATA BUS
MCU Status Register (MCUSR)
PORF BORF EXTRF WDRF
Power-on Reset Circuit
BODLEVEL [2..0]
Brown-out Reset Circuit
Pull-up Resistor
SPIKE FILTER
RSTDISBL Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
36
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 20. (1)
( ) ( )(2) RESET RESET 1. 2. VPOT TBD TBD 0.1 TBD TBD TBD TBD 0.9 2.5 V V V s
VPOT
VRST tRST Notes:
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2545A-AVR-09/03
(POR) Table20 VCC POR POR POR CC V VCC RESET Figure 17. MCU RESET VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 18. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
38
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
RESET ( Table20) VRST( ) tTOUT MCU RSTDISBL P256Table120 Figure 19.
CC
ATmega48/88/168 BOD(Brown-out Detection) VCC BODLEVEL BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 Table 21. BODLEVEL (1)
BODLEVEL 2..0 111 110 101 100 011 010 001 000 Note: 1. VBOT VCC VCC = VBOT ATmega48V/88V/168V BODLEVEL = 110 BODLEVEL = 101 ATmega48/88/168 BODLEVEL = 101 BODLEVEL = 101 VBOT VBOT 1.8 2.7 4.3 V VBOT BOD
Table 22.
VHYST tBOD 50 mV ns
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2545A-AVR-09/03
BOD VCC (VBOT- Figure20)BOD VCC (VBOT+ Figure20) tTOUT MCU VCC Table20 tBODBOD Figure 20.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
1 CK tTOUT P44 Figure 21.
CC
CK
MCU --MCUSR
MCU MCU
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
* 7..4: Res: ATmega48/88/168 "0" * 3 - WDRF: "0"
40
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* 2 - BORF: "0" * 1 - EXTRF: "0" * 0 - PORF: "0" MCUSR
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2545A-AVR-09/03
ATmega48/88/168 ADC Table23 1. BOD ( BODLEVEL [2..0] ) 2. (ACSR ACBG ) 3. ADC BOD ACBG ADC Table 23. (1)
VBG tBG IBG Note: 1. TBD TBD TBD 1.0 1.1 40 10 1.2 70 TBD V s A
42
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
128 kHz P44Table26 WDR 10 ATmega48/88/168 P44Table26 WDTON 2 Table 24. P47"" Table 24. WDTON WDT
WDTON 1 2 WDT WDT
Figure 22.
OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K
128kHz OSCILLATOR
WATCHDOG RESET WDE
WDP0 WDP1 WDP2 WDP3
MCU RESET
WDIF INTERRUPT
WDIE
-- WDTCSR
/
7 WDIF R/W 0
6 WDIE R/W 0
5 WDP3 R/W 0
4 WDCE R/W 0
3 WDE R/W X
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCSR
* 7 - WDIF: WDIF "1" WDIF SREG I WDIE MCU * 6 - WDIE: WDIE "1" WDE I
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2545A-AVR-09/03
WDE WDIE WDIE WDIE Table 25.
WDE 0 0 1 1 WDIE 0 1 0 1
* Bit 4 - WDCE: WDE WDCE 4 WDE WDCE P47" " * 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" 2 P47" " 1 WDE MCUSR WDRF P41"MCU - MCUSR" WDRF WDRF WDE WDE WDRF
Note: BOD WDRF WDRF WDE
* 5, 2..0 - WDP3..0: 3, 2, 1, 0 WDP3..0 Table26 Table 26.
WDP3 0 0 0 0 0 0 0 WDP2 0 0 0 0 1 1 1 WDP1 0 0 1 1 0 0 1 WDP0 0 1 0 1 0 1 0 2K 4K 8K 16K 32K 64K 128K VCC = 5.0V 16 ms 32 ms 64 ms 0.125 s 0.25 s 0.5 s 1.0 s
44
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 26.
WDP3 0 1 1 1 1 1 1 1 1 WDP2 1 0 0 0 0 1 1 1 1 WDP1 1 0 0 1 1 0 0 1 1 WDP0 1 0 1 0 1 0 1 0 1 256K 512K 1024K VCC = 5.0V 2.0 s 4.0 s 8.0 s
C WDT ( ) (1)
WDT_off: ; MCUSR WDRF ldi out ldi out ldi out ret r16, (0<; WDCE WDE
; WDT
C (1)
void WDT_off(void) { /*MCUSR WDRF */ MCUSR = 0x00 /* WDCE WDE */ WDTCSR = (1<Note:
1.
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2545A-AVR-09/03

1 WDE ( ) 1. WDCE WDE "1" WDE "1" 2. 4 WDE WDP WDCE "0" 2 WDE "1" 1. WDCEWDE"1" WDE "1" 2. 4 WDCE "0" WDP WDE
46
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega48/88/168 AVR P11" " ATmega48 ATmega88 ATmega168 * * ATmega168 ATmega48 ATmega88 ATmega48 Boot Loader ATmega88 ATmega168 BOOTRST MCUCR IVSEL
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2545A-AVR-09/03
ATmega48
Table 27. ATmega48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 (2) 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 RESET INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIMER2 COMPA TIMER2 COMPB TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMPA TIMER0 COMPB TIMER0 OVF SPI, STC USART, RX USART, UDRE USART, TX ADC EE READY ANALOG COMP TWI SPM READY 0 1 0 1 2 / 2 A / 2 B / 2 / 1 / 1 A / 1 B / 1 / 0 A / 0 B / 0 SPI USART, Rx USART USART, Tx ADC EEPROM
48
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega48
0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 ; 0x01A RESET: 0x01B 0x01C 0x01D 0x01E 0x01F ... ... ldi out ldi out sei ... xxx ... r16, high(RAMEND); SPH,r16 r16, low(RAMEND) SPL,r16 ; ; RAM rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET EXT_INT0 EXT_INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY ; ; IRQ0 ; IRQ1 ; PCINT0 ; PCINT1 ; PCINT2 ; ; 2 A ; 2 B ; 2 ; 1 ; 1 A ; 1 B ; 1 ; 0 A ; 0 B ; 0 ; SPI ; USART RX ; USART UDR ; USART TX Complete ; ADC ; EEPROM ; ; ; SPM
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2545A-AVR-09/03
ATmega88
Table 28. ATmega88
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Notes: (2) 0x000(1) 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 RESET INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIMER2 COMPA TIMER2 COMPB TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMPA TIMER0 COMPB TIMER0 OVF SPI, STC USART, RX USART, UDRE USART, TX ADC EE READY ANALOG COMP TWI SPM READY 0 1 0 1 2 / 2 A / 2 B / 2 / 1 / 1 A / 1 B / 1 / 0 A / 0 B / 0 SPI USART, Rx USART USART, Tx Complete ADC EEPROM
1. BOOTRST MCU Boot Loader P241"Boot Loader RWW ATmega88 ATmega168" 2. MCUCRIVSEL Boot Boot
Table29 BOOTRST/IVSEL Boot
50
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 29. ATmega88(1)
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 0x000 0x000 Boot Boot 0x001 Boot + 0x001 0x001 Boot + 0x001
1. Boot P252Table109 BOOTRST "0" "1"
; ; IRQ0 ; IRQ1 ; PCINT0 ; PCINT1 ; PCINT2 ; ; 2 A ; 2 B ; 2 ; 1 ; 1 A ; 1 B ; 1 ; 0 A ; 0 B ; 0 ; SPI ; USART RX ; USART UDR ; USART TX ; ADC ; EEPROM ; ; ; SPM
ATmega88
0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 ; 0x01A RESET: 0x01B 0x01C 0x01D 0x01E 0x01F ... ... ldi out ldi out sei ... rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET EXT_INT0 EXT_INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY
r16, high(RAMEND); SPH,r16 r16, low(RAMEND) SPL,r16 ; xxx ... ; RAM
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2545A-AVR-09/03
BOOTRST Boot 2K MCUCR IVSEL ATmega88
0x000 0x001 0x002 0x003 0x004 0x005 ; .org 0xC01 0xC01 0xC02 ... 0xC19 rjmp rjmp ... rjmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM
BOOTRST Boot 2K ATmega88
.org 0x001 0x001 0x002 ... 0x019 ; .org 0xC00 0xC00 RESET: ldi 0xC01 0xC02 0xC03 0xC04 0xC05 out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM rjmp rjmp ... rjmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM
52
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
BOOTRST Boot 2K MCUCR IVSEL ATmega88
; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM rjmp rjmp rjmp ... rjmp RESET EXT_INT0 EXT_INT1 ... SPM_RDY ; ; IRQ0 ; IRQ1 ; ; SPM
ATmega168
Table 30. ATmega168
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (2) 0x0000(1) 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 RESET INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIMER2 COMPA TIMER2 COMPB TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMPA TIMER0 COMPB TIMER0 OVF SPI, STC USART, RX USART, UDRE USART, TX 0 1 0 1 2 / 2 A / 2 B / 2 / 1 / 1 A / 1 B / 1 / 0 A / 0 B / 0 SPI USART Rx USART USART Tx
53
2545A-AVR-09/03
Table 30. ATmega168 (Continued)
22 23 24 25 26 Notes: (2) 0x002A 0x002C 0x002E 0x0030 0x0032 ADC EE READY ANALOG COMP TWI SPM READY ADC EEPROM SPM
1. BOOTRST MCU Boot Loader P241"Boot Loader RWW ATmega88 ATmega168" 2. MCUCRIVSEL Boot Boot
Table31 BOOTRST/IVSEL Boot Table 31. ATmega168(1)
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 0x000 0x000 Boot Boot 0x001 Boot + 0x0002 0x001 Boot + 0x0002
1. Boot P252Table109 BOOTRST "0" "1"
jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp ; ; IRQ0 ; IRQ1 ; PCINT0 ; PCINT1 ; PCINT2 ; ; 2 A ; 2 B ; 2 ; 1 ; 1 A ; 1 B ; 1 ; 0 A ; 0 B ; 0 ; SPI ; USART RX
ATmega168
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 RESET EXT_INT0 EXT_INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC
54
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 ; 0x0033RESET: 0x0034 0x0035 0x0036 0x0037 0x0038 ... ... ldi out ldi out sei ... xxx ... r16, high(RAMEND); SPH,r16 r16, low(RAMEND) SPL,r16 ; ; RAM jmp jmp jmp jmp jmp jmp jmp USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY ; USART UDR ; USART TX ; ADC ; EEPROM ; ; ; SPM
BOOTRST Boot 2K MCUCR IVSEL ATmega168
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 ; .org 0xC02 0x1C02 0x1C04 ... 0x1C32 jmp jmp ... jmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM
55
2545A-AVR-09/03
BOOTRST Boot 2K ATmega168
.org 0x0002 0x0002 0x0004 ... 0x0032 ; .org 0x1C00 0x1C00 RESET: ldi 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM jmp jmp ... jmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM
ATmega168 BOOTRST Boot2K MCUCRIVSEL ATmega168
; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C32 ; 0x1C33 0x1C34 0x1C35 0x1C36 0x1C37 0x1C38 RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM jmp jmp jmp ... jmp RESET EXT_INT0 EXT_INT1 ... SPM_RDY ; ; IRQ0 ; IRQ1 ; ; SPM
Boot ATmega88 ATmega168 MCU --MCUCR
/
7 JTD R/W 0
6 - R 0
5 - R 0
4 PUD R/W 0
3 - R 0
2 - R 0
1 IVSEL R/W 0
0 IVCE R/W 0 MCUCR
* Bit 1 - IVSEL: IVSEL"0" FlashIVSEL"1" Boot Boot BOOTSZ P241"Boot Loader RWW ATmega88 ATmega168" IVSEL 1. IVCE 2. 4 IVSEL IVCE "0"
56
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
IVCE IVSEL IVSEL IVCE 4 I
Note: Boot Loader BootBLB02 Boot BLB12 Boot Loader Boot P241"Boot Loader RWW ATmega88 ATmega168"
ATmega48 * 0 - IVCE: IVSEL IVCE IVCE 4 IVSEL IVCE IVCE
Move_interrupts: ; ldi out ldi out ret r16, (1<; boot
C
void Move_interrupts(void) { /* */ MCUCR = (1< ATmega48
57
2545A-AVR-09/03
I/O
I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure23 P275" " Figure 23. I/O
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
: "x" "n" PORTB3 B 3 PORTxn I/O P75"I/O " I/O : - PORTx - DDRx - PINx / PINx "1" "0" "1" MCUCR PUD I/O P59" I/O " P64" " I/O
I/O
I/O Figure24 Pxn I/O
58
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 24. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
RESET SLEEP RRx WRx
WPx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD
DDxn PORTxn PINxn P75"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0")

DDRxn PINxn "1" PORTxn "0" "1" SBI ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) MCUCR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b10)
DATA BUS
59
2545A-AVR-09/03
Table32 Table 32.
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD( MCUCR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure24 PINxn Figure25 tpd,max tpd,min Figure 25.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
60
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
SYNC LATCH PINxn tpd,max tpd,min 1/2 11/2 Figure26 out in nop out SYNC LATCH tpd Figure 26.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx
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2545A-AVR-09/03
B 0 1 2 3 4 7 6 7 nop (1)
... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1<; nop
C
unsigned char i; ... /* */ /* */ PORTB = (1<Note:
1. 0 6 7 1 2 3 0 1
Figure24 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P64" " ("1") " " "1" "0" "0" "1"
( )
62
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
VCC GND
I/O Figure27 Figure24 AVR Figure 27. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
PTOExn WPx WRx RRx
DIEOExn DIEOVxn
1 0
Q CLR
RESET
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD
DATA BUS
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2545A-AVR-09/03
Table33 Figure27 Table 33.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE PUOV / / DDxnPORTxn PUD DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn PTOE DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV PTOE DIEOE
DIEOV DI
AIO
/

64
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
MCU --MCUCR
/ 7 JTD R/W 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* 4 - PUD: PUD DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P60" " B B Table34. Table 34. B
PB7 XTAL2 ( 2) TOSC2 ( 2) PCINT7 ( 7) XTAL1 ( 1 ) TOSC1 ( 1) PCINT6 ( 6) SCK (SPI ) PCINT5 ( 5) MISO (SPI / ) PCINT4 ( 4) MOSI (SPI / ) OC2A ( / 2 A ) PCINT3 ( 3) SS (SPI ) OC1B ( / 1 B ) PCINT2 ( 2) OC1A ( / 1 A ) PCINT1 ( 1) ICP1 ( / 1 ) CLKO ( ) PCINT0 ( 0)
PB6
PB5 PB4
PB3
PB2
PB1
PB0
* XTAL2/TOSC2/PCINT7 - B, 7 XTAL2 2 I/O TOSC2 2 RC ASSR AS2 ASSR AS2 EXCLK / 2 PB7 I/O PCINT7 7 PB7 PB7 DDB7 PORTB7 PINB7 0
65
2545A-AVR-09/03
* XTAL1/TOSC1/PCINT6 - B, 6 XTAL1 1 RC I/O TOSC1 1 RC ASSR AS2 ASSR AS2 / 2 PB6 I/O PCINT6 6 PB6 PB6 DDB6 PORTB6 PINB6 "0" * SCK/PCINT5 - B, 5 SCK SPI SPI DDB5 SPI DDB5 SPI PORTB5 PCINT5 5 PB5 * MISO/PCINT4 - B, 4 MISO SPI / SPI SPI DDB4 PB4 SPI DDB4 SPI PORTB4 PCINT4 4 PB4 * MOSI/OC2/PCINT3 - B, 3 MOSI SPI / SPI DDB3 PB3 SPI DDB3 SPI PORTB3 OC2PB3 / 2 PB3 (DDB3=1) PWM OC2 PWM PCINT3 3 PB3 * SS/OC1B/PCINT2 - B, 2 SS SPI DDB2 PB2 PB2 SPI SPI DDB2 SPI PORTB2 OC1B PB2 / 1 B PB2 (DDB2=1) PWM OC1B PWM PCINT2 2 PB2 * OC1A/PCINT1 - B, 1 OC1A PB1 / 1 A PB1 (DDB1=1) PWM OC1A PWM
66
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
PCINT1 1 PB1 * ICP1/CLKO/PCINT0 - B, 0 ICP1PB0 / 1 CLKO PB0 CKOUT PORTB0 DDB0 PCINT0 0 PB0 Table35 Table36 B P63Figure 27 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSISPI MSTR OUTPUT SPI SLAVE INPUT Table 35. PB7..PB4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE PB7/XTAL2/ TOSC2/PCINT7(1) INTRC * EXTCK+ AS2 0 INTRC * EXTCK+ AS2 0 0 0 INTRC * EXTCK + AS2 + PCINT7 * PCIE0 (INTRC + EXTCK) * AS2 PCINT7INPUT Oscillator Output PB6/XTAL1/ TOSC1/PCINT6(1) INTRC + AS2 0 INTRC + AS2 0 0 0 INTRC + AS2 + PCINT6 * PCIE0 INTRC * AS2 PCINT6INPUT Oscillator/Clock Input PB5/SCK/ PCINT5 SPE * MSTR PORTB5 * PUD SPE * MSTR 0 SPE * MSTR SCK OUTPUT PCINT5 * PCIE0 PB4/MISO/ PCINT4 SPE * MSTR PORTB4 * PUD SPE * MSTR 0 SPE * MSTR SPI SLAVE OUTPUT PCINT4 * PCIE0
DIEOV DI AIO
1 PCINT5 INPUT SCK INPUT -
1 PCINT4 INPUT SPI MSTRINPUT -
67
2545A-AVR-09/03
Notes:
1. INTRCRC(CKSEL )EXTCK ( CKSEL )
Table 36. PB3..PB0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI PB3/MOSI/ OC2/PCINT3 SPE * MSTR PORTB3 * PUD SPE * MSTR 0 SPE * MSTR + OC2A ENABLE SPI MSTR OUTPUT + OC2A PCINT3 * PCIE0 1 PCINT3 INPUT SPI SLAVE INPUT - PB2/SS/ OC1B/PCINT2 SPE * MSTR PORTB2 * PUD SPE * MSTR 0 OC1B ENABLE OC1B PCINT2 * PCIE0 1 PCINT2 INPUT SPI SS - PB1/OC1A/ PCINT1 0 0 0 0 OC1AENABLE OC1A PCINT1 * PCIE0 1 PCINT1 INPUT PB0/ICP1/ PCINT0 0 0 0 0 0 0 PCINT0 * PCIE0 1 PCINT0 INPUT ICP1 INPUT -
AIO
-
C
C Table37 Table 37. C
PC6 RESET ( ) PCINT14 ( 14) ADC5 (ADC 5) SCL ( ) PCINT13 ( 13) ADC4 (ADC 4) SDA ( / ) PCINT12 ( 12) ADC3 (ADC 3) PCINT11 ( 11) ADC2 (ADC 2) PCINT10 ( 10) ADC1 (ADC 1) PCINT9 ( 9) ADC0 (ADC 0) PCINT8 ( 8)
PC5
PC4
PC3 PC2 PC1 PC0
68
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* RESET/PCINT14 - C, 6 RESET RSTDISBL I/O BOD RSTDISBL I/O PC6 DDC6 PORTC6 PINC6 0 PCINT14 14 PC6 * SCL/ADC5/PCINT13 - C, 5 SCL TWCR TWEN "1" TWI PC5 I/O TWI 50 ns PC5 ADC 5 ADC 5 PCINT13 13 PC5 * SDA/ADC4/PCINT12 - C, 4 SDA TWCR TWEN 1 TWI PC5I/O TWI 50 ns PC4 ADC 4 ADC 4 PCINT12 12 PC4 * ADC3/PCINT11 - C, 3 PC3 ADC 3 ADC 3 PCINT11 11 PC3 * ADC2/PCINT10 - C, 2 PC2 ADC 2 ADC 2 PCINT10 10 PC2 * ADC1/PCINT9 - C, 1 PC1 ADC 1 ADC 1 PCINT9 9 PC1 * ADC0/PCINT8 - C, 0 PC0 ADC 0 ADC 0 PCINT8 8 PC0
69
2545A-AVR-09/03
Table38 Table39 C P63Figure 27 Table 38. PC6..PC4(1)
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: PC6/RESET/PCINT14 RSTDISBL 1 RSTDISBL 0 0 0 RSTDISBL + PCINT14 * PCIE1 RSTDISBL PCINT14 INPUT RESET INPUT PC5/SCL/ADC5/PCINT13 TWEN PORTC5 * PUD TWEN SCL_OUT TWEN 0 PCINT13 * PCIE1 + ADC5D PCINT13 * PCIE1 PCINT13 INPUT ADC5 INPUT / SCL INPUT PC4/SDA/ADC4/PCINT12 TWEN PORTC4 * PUD TWEN SDA_OUT TWEN 0 PCINT12 * PCIE1 + ADC4D PCINT12 * PCIE1 PCINT12 INPUT ADC4 INPUT / SDA INPUT
1. PC4 PC5 AIO TWI
Table 39. PC3..PC0
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC3/ADC3/ PCINT11 0 0 0 0 0 0 PCINT11 * PCIE1 + ADC3D PCINT11 * PCIE1 PCINT11 INPUT ADC3 INPUT PC2/ADC2/ PCINT10 0 0 0 0 0 0 PCINT10 * PCIE1 + ADC2D PCINT10 * PCIE1 PCINT10 INPUT ADC2 INPUT PC1/ADC1/ PCINT9 0 0 0 0 0 0 PCINT9 * PCIE1 + ADC1D PCINT9 * PCIE1 PCINT9 INPUT ADC1 INPUT PC0/ADC0/ PCINT8 0 0 0 0 0 0 PCINT8 * PCIE1 + ADC0D PCINT8 * PCIE1 PCINT8 INPUT ADC0 INPUT
70
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
D D Table40 Table 40. D
PD7 AIN1 ( ) PCINT23 ( 23) AIN0 ( ) OC0A ( / 0 A ) PCINT22 ( 22) T1 ( / 1 ) OC0B ( / 0 B ) PCINT21 ( 21) XCK (USART / ) T0 ( / 0 ) PCINT20 ( 20) INT1 ( 1 ) OC2B ( / 2 B ) PCINT19 ( 19) INT0 ( 0 ) PCINT18 ( 18) TXD (USART ) PCINT17 ( 17) RXD (USART ) PCINT16 ( 16)
PD6
PD5
PD4
PD3
PD2 PD1 PD0
* AIN1/OC2B/PCINT23 - D, 7 AIN1 PD7 PCINT23 23 PD7 * AIN0/OC0A/PCINT22 - D, 6 AIN0 PD6 OC0A PD6/0A PD6 (DDD6=1) PWM OC0A PWM PCINT22 22 PD6 * T1/OC0B/PCINT21 - D, 5 T1 / 1 OC0B PD5/0B PD5 (DDD5=1) PWM OC0B PWM PCINT21 21 PD5
71
2545A-AVR-09/03
* XCK/T0/PCINT20 - D, 4 XCK USART T0 / 0 PCINT20 20 PD4 * INT1/OC2B/PCINT19 - D, 3 INT1 1PD3 OC2B PD3/0B PD3 (DDD3=1) PWM OC2B PWM PCINT19 19 PD3 * INT0/PCINT18 - D, 2 INT0 0PD2 PCINT18 18 PD2 * TXD/PCINT17 - D, 1 TXD (USART ) USART DDD1 PCINT17 17 PD1 * RXD/PCINT16 - D, 0 RXD ( USART ) USART DDD0 PORTD0 PCINT16 16 PD0 Table41 Table42 D P63Figure 27 Table 41. PD7..PD4
PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI PD7/AIN1 /PCINT23 0 0 0 0 0 0 PCINT23 * PCIE2 1 PCINT23 INPUT PD6/AIN0/ OC0A/PCINT22 0 0 0 0 OC0A ENABLE OC0A PCINT22 * PCIE2 1 PCINT22 INPUT PD5/T1/OC0B/ PCINT21 0 0 0 0 OC0B ENABLE OC0B PCINT21 * PCIE2 1 PCINT21 INPUT T1 INPUT - PD4/XCK/ T0/PCINT20 0 0 0 0 UMSEL XCK OUTPUT PCINT20 * PCIE2 1 PCINT20 INPUT XCK INPUT T0 INPUT -
AIO
AIN1 INPUT
AIN0 INPUT
72
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 42. PD3..PD0
PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD3/OC2B/INT1/ PCINT19 0 0 0 0 OC2B ENABLE OC2B INT1 ENABLE + PCINT19 * PCIE2 1 PCINT19 INPUT INT1 INPUT - PD2/INT0/ PCINT18 0 0 0 0 0 0 INT0 ENABLE + PCINT18 * PCIE1 1 PCINT18 INPUT INT0 INPUT - PD1/TXD/ PCINT17 TXEN 0 TXEN 1 TXEN TXD PCINT17 * PCIE2 1 PCINT17 INPUT - PD0/RXD/ PCINT16 RXEN PORTD0 * PUD RXEN 0 0 0 PCINT16 * PCIE2 1 PCINT16 INPUT RXD -
73
2545A-AVR-09/03
I/O
B --PORTB
/ 7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B --DDRB
/
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
B --PINB
/
7 PINB7 R N/A
6 PINB6 R N/A
5 PINB5 R N/A
4 PINB4 R N/A
3 PINB3 R N/A
2 PINB2 R N/A
1 PINB1 R N/A
0 PINB0 R N/A PINB
C --PORTC
/
7
-
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
C --DDRC
/
7 - R 0
6 DDC6 R/W 0
5 DDC5 R/W 0
4 DDC4 R/W 0
3 DDC3 R/W 0
2 DDC2 R/W 0
1 DDC1 R/W 0
0 DDC0 R/W 0 DDRC
C --PINC
/
7 - R 0
6 PINC6 R N/A
5 PINC5 R N/A
4 PINC4 R N/A
3 PINC3 R N/A
2 PINC2 R N/A
1 PINC1 R N/A
0 PINC0 R N/A PINC
D --PORTD
/
7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D --DDRD
/
7 DDD7 R/W 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
D --PIND
/
7 PIND7 R N/A
6 PIND6 R N/A
5 PIND5 R N/A
4 PIND4 R N/A
3 PIND3 R N/A
2 PIND2 R N/A
1 PIND1 R N/A
0 PIND0 R N/A PIND
74
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
INT0 INT1 PCINT23..0 INT0 INT1 PCINT23..0 PCINT23..16 PCI2 PCINT14..8 PCI1 PCINT7..0 PCI0PCMSK2PCMSK1 PCMSK0 PCINT23..0 INT0 INT1 A - EICRA INT0 INT1 INT0 INT1 I/O(P23"" ) INT0INT1 ( ) I/O MCU MCU MCU SUT CKSEL P23" " A--EICRA A
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 EICRA
* 7..4 - Res: ATmega48/88/168 "0" * 3, 2 - ISC11, ISC10: 1 1 0 1 INT1 SREG I Table43 MCU INT1
75
2545A-AVR-09/03
Table 43. 1
ISC11 0 0 1 1 ISC10 0 1 0 1 INT1 INT1 INT1 INT1
* 1, 0 - ISC01, ISC00: 0 1 0 0 INT0 SREG I Table44 MCU INT0 Table 44. 0
ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0
--EIMSK
/
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 INT1 R/W 0
0 INT0 R/W 0 EIMSK
* 7..2 - Res: ATmega48/88/168 "0" * 1 - INT1: 1 INT1 "1" SREG I - EICRA (ISC11 ISC10) INT1 INT1 INT1 * 0 - INT0: 0 INT0 "1" SREG I - EICRA (ISC11 ISC10) INT0 INT0 INT0 --EIFR
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 INTF1 R/W 0 0 INTF0 R/W 0 EIFR
76
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* 7..2 - Res: ATmega48/88/168 "0" * 1 - INTF1: 1 INT1 INTF1 SREG I EIMSK INT1 "1" MCU "1" INT1 INTF1 * 0 - INTF0: 0 INT0 INTF0 SREG I EIMSK INT0 "1" MCU "1" INT0 INTF0 -- PCICR
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 PCIE2 R/W 0 1 PCIE1 R/W 0 0 PCIE0 R/W 0 PCICR
* 7..3 - Res: ATmega48/88/168 "0" * 2 - PCIE2: 2 PCIE2 SREG I "1" PCINT23..16 PCI2 PCINT23..16 PCMSK2 * 1 - PCIE1: 1 PCIE1 SREG I "1" PCINT14..8 PCI1 PCINT14..8 PCMSK1 * 0 - PCIE0: 0 PCIE0 SREG I "1" PCINT7..0 PCI0 PCINT7..0 PCMSK0 -- PCIFR
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 PCIF2 R/W 0 1 PCIF1 R/W 0 0 PCIF0 R/W 0 PCIFR
* 7..3 - Res: ATmega48/88/168 "0"
77
2545A-AVR-09/03
* 2 - PCIF2: 2 PCINT23..16 PCIF2 "1" SREG I I PCICR PCIE2 "1" MCU "1" * 1 - PCIF1: 1 PCINT14..8 PCIF1 "1" SREG I I PCICR PCIE1 "1" MCU "1" * 0 - PCIF0: 0 PCINT7..0 PCIF0 "1" SREG I I PCICR PCIE0 "1"MCU "1" 2-- PCMSK2
/ 7
PCINT23
6
PCINT22
5
PCINT21
4
PCINT20
3
PCINT19
2
PCINT18
1
PCINT17
0
PCINT16 PCMSK2
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7..0 - PCINT23..16: 23..16 PCINT23..16I/O PCINT23..16 PCICR PCIE2 PCINT23..16 1-- PCMSK1
/ 7
-
6
PCINT14
5
PCINT13
4
PCINT12
3
PCINT11
2
PCINT10
1
PCINT9
0
PCINT8 PCMSK1
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7 - Res: ATmega48/88/168 "0" * 6..0 - PCINT14..8: 14..8 PCINT14..8 I/O PCINT14..8 PCICR PCIE1 PCINT14..8 0-- PCMSK0
/ 7 PCINT7 R/W 0 6 PCINT6 R/W 0 5 PCINT5 R/W 0 4 PCINT4 R/W 0 3 PCINT3 R/W 0 2 PCINT2 R/W 0 1 PCINT1 R/W 0 0 PCINT0 R/W 0 PCMSK0
* 7..0 - PCINT7..0: 7..0 PCINT7..0 I/O PCINT7..0 PCICR PCIE0 PCINT7..0
78
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
PWM 8 / 0
T/C0 8 / PWM ( ) * * * ( ) * PWM * PWM * * (TOV0, OCF0A OCF0B) Figure288/ P2"ATmega48/88/168 " CPU I/O I/O P89"8 / " Figure 28. 8 T/C
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn T/C Oscillator TOP BOTTOM Prescaler clkI/O TOSC2 TOSC1
Timer/Counter TCNTn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Value
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB
TCCRnA
TCCRnB
"n" T/C 0 "x" A B TCNT0 T/C0 Table45
79
2545A-AVR-09/03
Table 45. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0A
T/C(TCNT0) (OCR0A OCR0B) 8 ( Int.Req. ) TIFR0 TIMSK0 TIFR0 TIMSK0 T/C T0 ( )T/C T/C clkT0 (OCR0A OCR0B) T/C PWM (OCR0A OCR0B) P105" " (OCF0A OCF0B)
T/C
T/C T/C TCCR0B CS02:0 P95"T/C0 T/C1 " 8 T/C Figure29 Figure 29.
DATA BUS
TOVn (Int.Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0)
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) 80
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
T/C (TCCR0A)WGM01WGM00T/C(TCCR0B) WGM02 OC0A OC0B P84" " T/CTOV0WGM02:0 TOV0CPU
8TCNT0OCR0AOCR0B TCNT0 OCR0A OCR0B OCF0A OCR0B OCIE0A = 1 SREG I CPU OCF0A "1" WGM02:0 COM0x1:0 max bottom (P84" " ) Figure30 Figure 30.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnx1:0
PWM OCR0x OCR0x top bottom PWM OCR0x CPU OCR0x CPU OCR0x PWM FOC0x "1" OCF0x / OC0x (COM0x1:0 OC0x "0""1" ) CPU TCNT0 OCR0x TCNT0
TCNT0
81
2545A-AVR-09/03
TCNT0 TCNT0 T/C TCNT0 OCR0x TCNT0 BOTTOM OC0x OC0x FOC0x OC0x COM0x1:0 COM0x1:0
COM0x1:0 COM0x1:0 (OC0x) COM0x1:0 OC0x Figure31 COM0x1:0 I/O I/O I/O COM0x1:0 I/O (DDR PORT) OC0xOC0x OC0x OC0x Figure 31.
COMnx1 COMnx0 FOCn
Waveform Generator
D
Q
1 OCnx Pin
OCnx D
DATA BUS
0
Q
PORT D Q
DDR
clk I/O
COM0x1:0 I/O OC0x DDR OC0x DDR_OC0x OC0x COM0x1:0 P89"8 / " COM0x1:0 CTC PWM COM0x1:0 = 0 OC0x PWMP88Table46 PWMP88Table47 PWM P88Table48 COM0x1:0 PWM FOC0x
82
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
- T/C - (WGM02:0) (COM0x1:0) COM0x1:0 PWM PWM COM0x1:0 (P83" " ) P87"T/C " (WGM02:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0 CPU CTC( ) CTC (WGM02:0 = 2) OCR0A TCNT0 OCR0A OCR0A TOP CTC Figure32 TCNT0TCNT0OCR0A TCNT0 Figure 32. CTC
OCnx Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
OCF0A TOP TOP CTC TOP BOTTOM OCR0A TCNT0 0xFF 0x00 OCF0A CTC OC0A COM0A1:0 = 1 OC0A fOC0 = fclk_I/O/2 (OCR0A = 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 64 1024) TOV0 MAX 0x00 83
2545A-AVR-09/03
PWM
PWM (WGM02:0 = 3 7) PWM PWM PWM BOTTOM TOP BOTTOM WGM2:0 = 3 TOP 0xFF WGM2:0 = 7 TOP OCR0A OC0x TCNT0 OCR0x BOTTOM OC0x PWM PWM PWM DAC ( ) PWM MAX Figure33 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 33. PWM
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
TOP T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM 3 PWM WGM02 COM0A1:0"1"OC0A OC0B ( P89Table50 ) OC0x PWM OC0x OCR0x TCNT0 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 64 256 1024) OCR0A PWM OCR0A BOTTOM MAX+1OCR0AMAX COM0A1:0 OC0A (COM0x1:0 = 1) 50% OCR0A0foc2 = fclk_I/O/2 CTC OC0A PWM 84
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
PWM PWM (WGM02:0 = 1 5) PWM BOTTOM TOP TOP BOTTOM WGM2:0 = 1 TOP 0xFF WGM2:0 = 5 TOPOCR0A TOPTCNT0 OCR0x OC0x BOTTOM TCNT0 OCR0x OC0x PWM TOP TCNT0 TOP Figure34 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 34. PWM
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM COM0x1:0 3 PWM WGM02 COM0A "1" OC0A OC0B (P89Table51 ) OC0x OCR0x TCNT0 OC0x PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0A PWM PWM OCR0A BOTTOM OCR0A MAX PWM
85
2545A-AVR-09/03
Figure34 2 OCnx BOTTOM * Figure34 OCRnx MAX OCR0A MAX OCn BOTTOM T/C MAX OCnx OCnx OCRnx BOTTOM OCnx OCnx
*
T/C
T/C clkT0 Figure35 T/C PWM MAX Figure 35. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure36 Figure 36. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure37OCF0B CTC PWMOCF0A OCR0A TOP
86
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 37. T/C OCF0x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure38 CTCPWMOCF0ATCNT0 OCR0A TOP Figure 38. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
87
2545A-AVR-09/03
8 /
T/C A--TCCR0A
/ 7
COM0A1
6
COM0A0
5
COM0B1
4
COM0B0
3
-
2
-
1
WGM01
0
WGM00 TCCR0A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* 7:6 - COM0A1:0: A OC0A COM0A1:0 OC0A 1 OC0A COM0A1:0WGM02:0 Table46 WGM02:0 CTC ( PWM ) COM0A1:0 Table 46. PWM
COM0A1 0 0 1 1 COM0A0 0 1 0 1 OC0A OC0A OC0A OC0A
Table47 WGM01:0 PWM COM0A1:0 Table 47. PWM (1)
COM0A1 0 0 1 1 Note: COM0A0 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A TOP OC0A OC0A TOP OC0A
1. OCR0A TOP COM0A1 TOP OC0A P85" PWM "
Table48 WGM02:0 PWM COM0A1:0 Table 48. PWM (1)
COM0A1 0 0 1 1 COM0A0 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A OC0A OC0A OC0A
88
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Note: 1. OCR0A TOP COM0A1 TOP OC0A P111" PWM "
* 5:4 - COM0B1:0: B OC0B COM0B1:0 OC0B 1 OC0B COM0B1:0 WGM02:0 Table49 WGM02:0 CTC COM0B1:0 Table 49. PWM
COM0B1 0 0 1 1 COM0B0 0 1 0 1 OC0B OC0B OC0B OC0B
Table50 WGM02:0 PWM COM0B1:0 Table 50. PWM (1)
COM0B1 0 0 1 1 Note: COM0B0 0 1 0 1 OC0B OC0B TOP OC0B OC0B TOP OC0B
1. OCR0B TOP COM0B1 TOP OC0B P85" PWM "
Table51 WGM02:0 PWM COM0B1:0 Table 51. PWM (1)
COM0B1 0 0 1 1 Note: COM0B0 0 1 0 1 OC0B OC0B OC0B OC0B OC0B
1. OCR0B TOP COM0B1 TOP OC0B P86" PWM "
* 3, 2 - Res: ATmega48/88/168 "0"
89
2545A-AVR-09/03
* 1:0 - WGM01:0: TCCR0B WGM02 TOP Table52 T/C (CTC) PWM ( P84" " ) Table 52.
0 1 2 3 4 5 6 7 Notes: WGM02 0 0 0 0 1 1 1 1 WGM01 0 0 1 1 0 0 1 1 WGM00 0 1 0 1 0 1 0 1 T/C PWM CTC PWM PWM PWM TOP 0xFF 0xFF OCRA 0xFF - OCRA - OCRA OCRx TOP TOP - TOP - TOP TOV (1)(2) MAX BOTTOM MAX MAX - BOTTOM - TOP
1. MAX = 0xFF 2. BOTTOM = 0x00
90
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
T/C B--TCCR0B
/ 7
FOC0A
6
FOC0B
5
-
4
-
3
WGM02
2
CS02
1
CS01
0
CS00 TCCR0B
W 0
W 0
R 0
R 0
R 0
R 0
R/W 0
R/W 0
* 7 - FOC0A: A FOC0A WGM PWM PWM TCCR0B 1 OC0A COM0A1:0 FOC0A COM0A1:0 FOC0A OCR0ATOPCTC FOC0A 0 * 6 - FOC0B: B FOC0B WGM PWM PWM TCCR0B 1 OC0B COM0B1:0 FOC0B COM0B1:0 FOC0B OCR0BTOPCTC FOC0B 0 * 5:4 - Res: ATmega48/88/168 "0" * 3 - WGM02: P89"T/C A - TCCR0A" * 2:0 - CS02:0: T/C Table 53.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0
91
2545A-AVR-09/03
T/C0 T0 T/C --TCNT0
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0
TCNT0[7:0]
T/C 8 TCNT0 TCNT0 TCNT0 OCR0x A--OCR0A
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0A R/W 0
OCR0A[7:0]
A 8 TCNT0 OC0A B--OCR0B
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0B R/W 0
OCR0B[7:0]
B 8 TCNT0 OC0B T/C --TIMSK0
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCIE0B R/W 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0
* 7..3 - Res: ATmega48/88/168 0 * 2 - OCIE0B: T/C B OCIE0B I "1" T/C B T/C TIFR0 OCF0B * 1 - OCIE0A: T/C0 A OCIE0A I "1" T/C0 A T/C0 TIFR0 OCF0A * 0 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR0 TOV0 T/C 0 --TIFR0
7 6 5 4 3 2 1 0
92
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
- / R 0 - R 0 - R 0 - R 0 - R 0 OCF0B R/W 0 OCF0A R/W 0 TOV0 R/W 0 TIFR0
* 7..3 - Res: ATmega48/88/168 0 * 2 - OCF0B: T/C0 B T/C OCR0B( 0B) OCF0B 1 SREG IOCIE0B(T/C B ) OCF0B * 1 - OCF0A: T/C0 A T/C0 OCR0A( 0A) OCF0A 1 SREG I OCIE0A(T/C0 ) OCF0A * 0 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 WGM02:0 Table52 P90" "
93
2545A-AVR-09/03
T/C0 T/C1
T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C
T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure39 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 39. T1/T0
Tn_sync (To Clock Select Logic)
Tn
D LE
Q
D
Q
D
Q
clk I/O
Synchronization Edge Detector
T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
94
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 40. T/C0 T/C1 (1)
clk I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. (T1/T0) Figure39.
T/C --GTCCR
/
7 TSM R/W 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 PSRASY R/W 0
0 PSRSYNC R/W 0 GTCCR
* 7 - TSM: T/C TSMT/C TSM PSR2 PSR10 / T/C / T/C TSM PSR2 PSR10 / * 0 - PSRSYNC: PSRSYNCT/C1T/C0 TSM T/C1T/C0
95
2545A-AVR-09/03
16 / 1
16T/C() * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1OCF1A OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16 T/C Figure41 P2"ATmega48/88/168 I/O " CPU I/O I/O I/O I/O P117"16 / " Figure 41. 16 T/C (1)
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Values
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB ICFn (Int.Req.) Edge Detector
( From Analog Comparator Ouput )
ICRn
Noise Canceler ICPn
TCCRnA
TCCRnB
Note:
1. P2Figure 1 P65Table34 P71Table40 T/C1
96
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
/ TCNT1 OCR1A/B ICR1 16 16 P99" 16 " T/C TCCR1A/B 8 CPU ( Int.Req.) TIFR1 TIMSK1 TIFR1 TIMSK1 T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWM OC1A/B P104" " OCF1A/B ICP1 ( P214" " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM Table 54.
BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1
97
2545A-AVR-09/03
16
TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 16 8 8 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16 (1)
... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H
C (1)
unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ...
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNT1 r17:r16 16 16 16 16 16
98
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TCNT1 OCR1A/B ICR1 (1)
TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ;
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNT1 r17:r16
99
2545A-AVR-09/03
TCNT1 OCR1A/B ICR1 (1)
TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ;
C (1)
void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
r17:r16 TCNT1 16
100
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
T/C
T/C T/C B(TCCR1B) (CS12:0) P95"T/C0 T/C1 " 16 T/C 16 Figure42 Figure 42.
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P107" " WGM13:0 TOV1 TOV1 CPU
T/C ICP1 Figure43 "n" /
101
2545A-AVR-09/03
Figure 43.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 ICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P99" 16 " 16 ICP1T/C1 ACSR ACIC CP1ACOT1(P94Figure 39 ), 4 ICR1 TOP T/C ICP1 4 4 TCCR1B ICNC1 ICR1 4
102
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1
16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P107" " ) A T/C TOP ( ) TOP Figure44 "n" (n = 1 T/C1) "x" (A/B) Figure 44.
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 103
2545A-AVR-09/03
) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P99" 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPU TCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1 BOTTOM OC1x OC1x FOC1x OC1x COM1x1:0 COM1x1:0
TCNT1
104
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure45 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x COM1x "0" Figure 45.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table55 Table56 Table57 OC1x COM1x1:0 P117"16/" COM1x1:0
105
2545A-AVR-09/03
COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P116Table55 PWM P116Table56 PWM P117Table57 . COM1x1:0 PWM FOC1x
- T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 ( P106" " ) P115" / "
(WGM13:0 = 0) (MAX = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU
106
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
CTC( ) CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTC Figure46 TCNT1TCNT1OCR1A ICR1 TCNT1 Figure 46. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 0xFFFF 0x0000 OCR1A ICR1 PWM OCR1A TOP (WGM13:0 = 15) OCR1A CTC OC0A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC2 = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000
107
2545A-AVR-09/03
PWM
PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM MAX BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure47 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 47. PWM
OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1
108
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P116Table ) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP ) N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM(0x0000) TOP+1 OCR1x TOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) foc2 = fclk_I/O/2 CTC OC1A PWM
109
2545A-AVR-09/03
PWM
PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11) TCNT1 TOP Figure48 OCR1AICR1TOPPWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 48. PWM
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure48 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP
110
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
T/C TOP TOP PWM OC1x PWM COM1x1:0 2 PWM COM1x1:0 3 PWM ( P117Table ) OC1x DDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A 50%
111
2545A-AVR-09/03
PWM
PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x Figure48 Figure49 PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure49 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 49. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A CF1 TOP BOTTOM TOPTOP TCNT1OCR1x Figure49 PWM OCR1x BOTTOM
112
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P117Table ) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1 OC1A 50%
113
2545A-AVR-09/03
/
/ clkT1 OCR1x OCR1x ( ) Figure50 OCF1x Figure 50. T/C OCF1x
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure51 Figure 51. T/C OCF1x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure52 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1
114
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 52. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure53 Figure 53. T/C fclk_I/O/8
clk I/O clk Tn
(clk /8) I/O
TCNTn
(CTC and FPWM)
TOP - 1 TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
115
2545A-AVR-09/03
16 /
T/C1 A--TCCR1A
/ 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
-
2
-
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* 7:6 - COM1A1:0: A * 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0) "1" OC1A(OC1B)I/O OC1A(OC1B) OC1A(OC1B) COM1x1:0 WGM13:0 Table55 WGM13:0 CTC ( PWM) COM1x1:0 Table 55. PWM
COM1A1/COM1B1 0 0 1 1 COM1A0/COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B ( )
Table56 WGM13:0 PWM COM1x1:0 Table 56. PWM(1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 15: OC1A OC1B WGM1 OC1A/OC1B OC1A/OC1BOC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P109" PWM "
116
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table57 WGM13:0 PWM PWM COM1x1:0 Table 57. PWM (1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 9 14: OC1A OC1B WGM1 OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 P111" PWM "
* 1:0 - WGM11:0: TCCR1B WGM13:2 ---- ( Table58) T/C ( ) (CTC) (PWM) (P107" " )
117
2545A-AVR-09/03
Table 58. (1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A OCR1x TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOV1 MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
1. CTC1 PWM11:0 WGM12:0
/
T/C1 B--TCCR1B
7 ICNC1 R/W 0
6 ICES1 R/W 0
5 - R 0
4 WGM13 R/W 0
3 WGM12 R/W 0
2 CS12 R/W 0
1 CS11 R/W 0
0 CS10 R/W 0 TCCR1B
* 7 - ICNC1: * ICNC1 ICP1 ICP1 4 4 4 * 6 - ICES1: ICP1 ICES "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * 5 - TCCR1B "0"
118
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* 4:3 - WGM13:2: TCCR1A * 2:0 - CS12:0: 3 T/C Figure50 Figure51 Table 59.
CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1
T1 1 T/C1 T/C1 C--TCCR1C
/ 7 FOC1A R/W 0 6 FOC1B R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1C
* 7 - FOC1A: A * 6 - FOC1B: B FOC1A/FOC1BWGM13:0PWM PWM TCCR1A FOC1A/FOC1B "1" COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 FOC1A/FOC1B OCR1A TOP CTC FOC1A/FOC1B T/C1--TCNT1H TCNT1L
7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0
TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 8 TEMPTEMP 16 P99" 16 " 119
2545A-AVR-09/03
TCNT1TCNT1OCR1x TCNT1 1A--OCR1AH OCR1AL
7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1B--OCR1BH OCR1BL
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNT1 OC1x 16 CPU 8 TEMP TEMP 16 P99" 16 "
120
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
1--ICR1H ICR1L
7 6 5 4 ICR1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 ICR1H ICR1L
ICR1[15:8]
ICP1(T/C1) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P99" 16 " T/C1 --TIMSK1
/ 7 - R 0 6 - R 0 5 ICIE1 R/W 0 4 - R 0 3 - R 0 2 OCIE1B R/W 0 1 OCIE1A R/W 0 0 TOIE1 R/W 0 TIMSK1
* 7, 6 - Res: ATmega48/88/168 0 * 5 - ICIE1: T/C1 "1" I "1" T/C1 T IFR1 ICF1 CPU T/C1 ( P48 " " ) * 4, 3 - Res: ATmega48/88/168 0 * 2 - OCIE1B: T/C1 B "1" I "1" T/C1 B TIFR1 OCF1B CPU T/C1 B ( P48 " " ) * 1 - OCIE1A: T/C1 A "1" I "1" T/C1 A TIFR1 OCF1A CPU T/C1 A ( P48 " " ) * 0 - TOIE1: T/C1 TOIE1 I "1" T/C1 TIFR1 TOV1 CPU T/C1 ( P44" " )
121
2545A-AVR-09/03
T/C1 --TIFR1
/
7 - R 0
6 - R 0
5 ICF1 R/W 0
4 - R 0
3 - R 0
2 OCF1B R/W 0
1 OCF1A R/W 0
0 TOV1 R/W 0 TIFR1
* 7, 6 - Res: ATmega48/88/168 0 * 5 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" * 4, 3 - Res: ATmega48/88/168 0 * 2 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * 1 - OCF1A: T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A A OCF1A "1" * 0 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P118Table58 OCF1A "1"
122
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
8 PWM / 2
T/C2 8 / * * ( ) * , (PWM) * * 10 * (TOV2 OCF2A) * 32 kHz I/O Figure54 8 T/C P2"ATmega48/88/168 " CPUI/O I/OI/O I/O P134"8 T/C " Figure 54. 8 T/C
Count Clear Direction Control Logic
TOVn (Int.Req.) clkTn T/C Oscillator TOP BOTTOM Prescaler clkI/O TOSC2 TOSC1
Timer/Counter TCNTn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Value
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB
TCCRnA
TCCRnB
/ TCNT2 OCR2A 8 ( Int.Req.) TIFR2 TIMSK2 TIFR2 TIMSK2 T/C2 TOSC1/2 ASSR T/C() T/C clkT2 OCR2A OCR2B TCNT2 PWM OC2A OCR2B P126"" OCF2AOCF2B 123
2545A-AVR-09/03
"n" / 2 (TCNT2T/C2) Table 60 Table 60. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR2A
T/C
T/C clkT2 MCU clkI/O ASSR AS2 TOSC1 TOSC2 P139" - ASSR" P142" / " 8 T/C Figure55 Figure 55.
DATA BUS
TOVn (Int.Req.)
TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
bottom
top
clkI/O
( ) count direction clear clkT2 top bottom TCNT2 1 1 TCNT2 ( ) T/C TCNT2 TCNT2 (0)
clkT2 clkT2 CS22:0 (CS22:0 = 0) clkT2 CPU TCNT2 CPU ( ) T/C (TCCR2A) WGM21 WGM20 TCCR2B WGM22 OC2A OC2B P128" " T/CTOV2WGM22:0 TOV2CPU
124
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
8TCNT2OCR2AOCR2B TCNT2 OCR2A OCR2B OCF2A OCF2B OCIE2A = 1 OCF2A "1" WGM22:0 COM2x1:0 max bottom (P128" " ) Figure56 Figure 56.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnX1:0
PWM OCR2x OCR2x top bottom PWM OCR2x CPU OCR2x CPU OCR2x PWM FOC2x "1" OCF2x / OC2x (COM2x1:0 OC2x ) CPU TCNT2 OCR2x TCNT2 TCNT2 TCNT2 T/C TCNT2 OCR2x TCNT2 BOTTOM OC2x OC2x FOC2x OC2x
TCNT2
125
2545A-AVR-09/03
COM2x1:0 COM2x1:0
126
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
COM2x1:0 COM2x1:0 (OC2x) COM2x1:0 OC2x Figure57 COM2x1:0 I/O I/O I/O COM2x1:0 I/O (DDR PORT) OC2x OC2x OC2x Figure 57.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM2x1:0 OC2x I/O OC2x (DDR) OC2x DDR_OC2x OC2x COM2x1:0 P134"8 T/C " COM2x1:0 CTC PWM COM2x1:0 = 0 OC2x PWM P134Table64 PWM P134Table65 PWM P134Table66 COM2x1:0 PWM FOC2x
- T/C - (WGM22:0) (COM2x1:0) COM2x1:0 PWM PWM COM2x1:0 (P128" " ) P132"T/C "
127
2545A-AVR-09/03
(WGM22:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV2 TOV2 9 TOV2 CPU
CTC( )
CTC (WGM22:0 = 2) OCR2A TCNT2 OCR2A OCR2A TOP CTCFigure58 TCNT2TCNT2OCR2A TCNT2 Figure 58. CTC
OCnx Interrupt Flag Set
TCNTn
OCnx (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
OCF2A TOP TOP CTC TOP BOTTOM OCR2A TCNT2 0xFF 0x00 OCR2A CTC OC2A COM2A1:0 = 1 OC2A fOC2 = fclk_I/O/2 (OC2A = 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 32 64 128 256 1024) TOV2 MAX 0x00 PWM PWM (WGM22:0 = 3 7) PWM PWM PWM BOTTOM MAX BOTTOM WGM2:0 = 3 TOP 0xFF and OCR2A when MGM2:0 = 7 TOP OCR2A OC2x TCNT2 OCR2x BOTTOM OC2x PWM
128
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
PWM PWM DAC ( ) PWM TOP Figure59 TCNT2 PWM PWM TCNT2 OCR2x TCNT2 Figure 59. PWM
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
TOP T/C TOV2 PWM OC2x PWM COM2x1:0 2 PWM 3 PWM WGM2:0 = 3 TOP0xFF MGM2:0 = 7 TOPOCR2A( P133Table62 ) OC2x PWM OC2x OCR2x TCNT2 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 32 64 128 256 1024) OCR2A PWM OCR2A BOTTOM MAX+1OCR2AMAX COM2A1:0 OC2x(COM2x1:0 = 1) 50% OCR2A 0 foc2 = fclk_I/O/2 CTC OC2A PWM PWM PWM (WGM22:0 = 1 5) PWM BOTTOM TOP TOP BOTTOM WGM2:0 = 3 TOP 0xFF MGM2:0 = 7 129
2545A-AVR-09/03
TOPOCR2A TOPTCNT2 OCR2x OC2x BOTTOM TCNT2 OCR2x OC2x PWM PWM 8 TOP TCNT2 TOP Figure60 TCNT2 PWM PWM TCNT2 OCR2x TCNT2 Figure 60. PWM
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV2 PWM OC2x PWM COM2x1:0 2 PWM COM2x1:0 3 PWM ( P133Table63 ) OC2x OCR2x TCNT2 OC2x PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 32 64 128 256 1024) OCR2A PWM PWM OCR2A BOTTOM OCR2A MAX PWM Figure60 2 OCn BOTTOM * Figure60 OCR2A MAX OCR2A MAX OCn BOTTOM
130
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
T/C MAX OCn OCn * OCR2A BOTTOM OCn OCn
T/C
T/C clkT2 clkI/O T/C Figure61 T/C PWM MAX Figure 61. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure62 Figure 62. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure63 ( CTC )OCF2A Figure 63. T/C OCF2A fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure64 CTC OCF2A TCNT2
131
2545A-AVR-09/03
Figure 64. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
132
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
8 T/C
T/C A--TCCR2A
/ 7
COM2A1
6
COM2A0
5
COM2B1
4
COM2B0
3
-
2
-
1
WGM21
0
WGM20 TCCR2A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* 7:6 - COM2A1:0: A OC2A COM2A1:0 OC2A 1 OC2A COM2A1:0 WGM22:0 Table61 WGM22:0 CTC ( PWM ) COM2A1:0 Table 61. PWM
COM2A1 0 0 1 1 COM2A0 0 1 0 1 OC2A OC2A OC2A OC2A
Table62 WGM21:0 PWM COM2A1:0 Table 62. PWM (1)
COM2A1 0 0 1 1 Note: COM2A0 0 1 0 1 OC2A WGM22 = 0 OC2A WGM22 = 1 OC2A OC2A TOP OC2A OC2A TOP OC2A
1. OCR2A TOP COM2A1 TOP P129" PWM "
Table63 WGM22:0 PWM COM2A1:0 Table 63. PWM (1)
COM2A1 0 0 1 1 Note: COM2A0 0 1 0 1 OC2A WGM22 = 0 OC2A WGM22 = 1 OC2A OC2A OC2A OC2A OC2A
1. OCR2A TOP COM2A1 TOP P130" PWM "
133
2545A-AVR-09/03
* 5:4 - COM2B1:0: B OC2B COM2B1:0 OC2B 1 OC2B COM2B1:0 WGM22:0 Table64 WGM22:0 CTC COM2B1:0 Table 64. PWM
COM2B1 0 0 1 1 COM2B0 0 1 0 1 OC2B OC2B OC2B OC2B
Table65 WGM22:0 PWM COM2B1:0 Table 65. PWM (1)
COM2B1 0 0 1 1 Note: COM2B0 0 1 0 1 OC2B OC2B TOP OC2B OC2B TOP OC2B
1. OCR2B TOP COM2B1 TOP P130" PWM "
Table66 WGM22:0 PWM COM2B1:0 Table 66. PWM (1)
COM2B1 0 0 1 1 Note: COM2B0 0 1 0 1 OC2B OC2B OC2B OC2B OC2B
1. OCR2B TOP COM2B1 TOP P130" PWM "
* 3, 2 - Res: ATmega48/88/168 "0" * 1:0 - WGM21:0: TCCR2B WGM22 TOP Table67 T/C (CTC) PWM P128" "
134
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 67.
0 1 2 3 4 5 6 7 Notes: WGM2 0 0 0 0 1 1 1 1 WGM1 0 0 1 1 0 0 1 1 WGM0 0 1 0 1 0 1 0 1 T/C PWM CTC PWM PWM PWM TOP 0xFF 0xFF OCRA 0xFF - OCRA - OCRA OCRx TOP TOP - TOP - TOP TOV (1)(2) MAX BOTTOM MAX MAX - BOTTOM - TOP
1. MAX= 0xFF 2. BOTTOM= 0x00
135
2545A-AVR-09/03
T/C B--TCCR2B
/
7
FOC2A
6
FOC2B
5
-
4
-
3
WGM22
2
CS22
1
CS21
0
CS20 TCCR2B
W 0
W 0
R 0
R 0
R 0
R 0
R/W 0
R/W 0
* 7 - FOC2A: A FOC2A WGM PWM PWM TCCR2B FOC2A 1 OC2A COM2A1:0 FOC2A COM2A1:0 FOC2A OCR2A TOP CTC FOC2A "0" * 6 - FOC2B: B FOC2B WGM PWM PWM TCCR2B FOC2B 1 OC2B COM2B1:0 FOC2B COM2B1:0 FOC2B OCR2BTOPCTC FOC2B "0" * 5:4 - Res: ATmega48/88/168 "0" * 3 - WGM22: P134"T/C A - TCCR2A" * 2:0 - CS22:0: T/C Table*NOTICE:
136
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
*NOTICE: CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 T/C clkT2S/1 ( ) clkT2S/8 ( ) clkT2S/32 ( ) clkT2S/64 ( ) clkT2S/128 ( ) clkT2S/256 ( ) clkT2S/1024 ( )
T/C0 T0 T/C0 T/C --TCNT2
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT2 R/W 0
TCNT2[7:0]
T/C 8 TCNT2 TCNT2 TCNT2 OCR2x A--OCR2A
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2A R/W 0
OCR2A[7:0]
A 8 TCNT2 OC2A B--OCR2B
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2B R/W 0
OCR2B[7:0]
B 8 TCNT2 OC2B
137
2545A-AVR-09/03
/
--ASSR
/ 7 - R 0 6 EXCLK R/W 0 5 AS2 R/W 0 4 TCN2UB R 0 3 OCR2AUB R 0 2 OCR2BUB R 0 1 TCR2AUB R 0 0 TCR2BUB R 0 ASSR
* 6 - EXCLK: EXCLK "1" TOSC1 32 kHz EXCLK "0" * 5 - AS2: T/C2 AS2"0"T/C2I/OclkI/OAS2"1"T/C2TOSC1 AS2 TCNT2 OCR2A OCR2B TCCR2A TCCR2B * 4 - TCN2UB: T/C2 T/C2 TCNT2TCN2UB TCNT2 TCN2UB TCN2UB 0 TCNT2 * 3 - OCR2AUB: 2 T/C2 OCR2A OCR2UB OCR2A OCR2AUB OCR2AUB 0 OCR2A * 2 - OCR2BUB: 2 T/C2 OCR2BOCR2BUB OCR2B OCR2BUB OCR2BUB 0 OCR2B * 1 - TCR2AUB: T/C 2 T/C2 TCCR2ATCR2AUB TCCR2A TCR2AUB TCR2AUB 0 TCCR2A * 0 - TCR2BUB: T/C 2 T/C2 TCCR2BTCR2BUB TCCR2B TCR2BUB TCR2BUB 0 TCCR2B TCNT2 OCR2AOCR2BTCCR2A TCCR2B TCNT2 OCR2A OCR2B TCCR2A TCCR2B / 2 T/C2 * TCNT2OCR2x TCCR2x 1. OCIE2x TOIE2 T/C2 2. AS2 3. TCNT2 OCR2x TCCR2x
138
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
4. TCN2xUB OCR2xUB TCR2xUB 5. T/C2 6. * * 4 TCNT2 OCR2x TCCR2x TOSC1 3 TCNT2 OCR2x ASSR T/C2 MCU ADC TCNT2 OCR2xTCCR2x MCUT/C2 T/C2 MCU OCR2x TCNT2 (OCR2xUB 0)MCU MCU T/C2 ADC TOSC1 TOSC1 1. TCCR2x TCNT2 OCR2x 2. ASSR 3. ADC * T/C2 32.768 kHz Standby 1 /Standby 1 T/C2 T/C2 ADC MCU 4 SLEEP TCNT2 TCNT2 TOSC TCNT2 I/O TOSC1 I/O TCNT2 TOSC1 TOSC1 TCNT2 1. OCR2x TCCR2x 2. 3. TCNT2 * 3
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCIE2B R/W 0 1 OCIE2A R/W 0 0 TOIE2 R/W 0 TIMSK2
*
*
*
*
/ 2 --TIMSK2
139
2545A-AVR-09/03
* 2 - OCIE2B: T/C2 B OCIE2B I "1" T/C2 B T/C2 TIFR2 OCF2B * 1 - OCIE2A: A OCIE2A I "1" T/C2 A T/C2 TIFR2 OCF2A * 0 - TOIE2: T/C2 TOIE2 I "1" T/C2 T/C2 TIFR2 TOV2 / 2 --TIFR2
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCF2B R/W 0 1 OCF2A R/W 0 0 TOV2 R/W 0 TIFR2
* 2 - OCF2B: 2 B T/C2 OCR2B( 2) OCF2B 1 SREG I OCIE2B OCF2B * 1 - OCF2A: 2 A T/C2 OCR2A( 2) OCF2A 1 SREG I OCIE2A OCF2A * 0 - TOV2: T/C2 T/C2 TOV2 TOV2 1 SREG ITOIE2A TOV2 PWM T/C2 0x00 TOV2
140
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
/
Figure 65. T/C2
clkI/O TOSC1 clkT2S Clear
clkT2S/8
10-BIT T/C PRESCALER
clkT2S/32 clkT2S/64 clkT2S/1024
0 GTCCR R/W 0
AS2
PSRASY
0
CS20 CS21 CS22
TIMER/COUNTER2 CLOCK SOURCE clkT2
T/C2 clkT2S clkT2 clkI/O ASSR AS2 T/C2 TOSC1 T/C2 RTC TOSC1 TOSC2 C ( 32.768 kHz ) TOSC1 T/C2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 clkT2S0 () GTCCRPSR2 T/C --GTCCR
/ 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 R/W 0
PSRASY PSRSYNC
* 1 - PSR2:T/C2 "1" T/C2 T/C2 TSM T/C P95"7 - TSM: T/C "
clkT2S/256
clkT2S/128
141
2545A-AVR-09/03
--SPI
SPI ATmega48/88/168 AVR ATmega48/88/168 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) USART SPI P177 "SPI USART" Figure 66. SPI (1)
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. SPI P2Figure 1 P65Table34
SPI Figure67 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI
142
ATmega48/88/168
2545A-AVR-09/03
SPI2X
ATmega48/88/168
SPIE SPDR SS SS SPI MISO SPI SPDR SCK SPDR SS SPIF SPCRSPISPIE SPDR Figure 67. SPI -
SHIFT ENABLE
SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSIMISOSCK SS Table68 P64" "
143
2545A-AVR-09/03
Table 68. SPI (1)
MOSI MISO SCK SS Note: SPI SPI
1. P66" B " SPI
SPI DDR_SPIDD_MOSI DD_MISODD_SCK MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB
144
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
(1)
SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; SPI fck/16
C (1)
void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1<Note:
1.
145
2545A-AVR-09/03
SPI (1)
SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1<; SPI
C (1)
void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1<Note:
1.
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SS
SPI SS SPI SS MISO ( ) SS SPI SS / SS SPI SPI (SPCR MSTR ) SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR "1" SPI SPI --SPCR
/ 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* 7 - SPIE: SPI SPSR SPIF SREG SPI * 6 - SPE: SPI SPE SPI SPI SPE * 5 - DORD: DORD LSB MSB * 4 - MSTR: / MSTR MSTR "1" SS MSTR SPSR SPIF MSTR * 3 - CPOL: CPOL SCK SCK Figure68 Figure69 CPOL Table 69. CPOL
CPOL 0 1
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* 2 - CPHA: CPHA SCK SCK Figure68 Figure69 CPHA Table 70. CPHA
CPHA 0 1
* 1, 0 - SPR1, SPR0: SPI SCK SPR1 SPR0 SCK fosc Table 71. SCK
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK
fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64
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ATmega48/88/168
SPI --SPSR
/ 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDRSPIF * 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * 5..1 - Res: ATmega48/88/168 0 * 0 - SPI2X: SPI SPI ( Table71) SCK CPU fosc /4 ATmega48/88/168 SPI EEPROM P270 SPI SPI --SPDR
/ 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X SPDR
SPI / SPI
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SCK 4 CPHA CPOL SPI Figure68 Figure69 SCK Table69 Table70 Table 72. CPOL
CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3
Figure 68. CPHA = 0 SPI
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 69. CPHA = 1 SPI
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
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ATmega48/88/168
USART0
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * USART SPI P177 "SPI USART" .
Figure70USART CPUI/OI/O Figure 70. USART (1)
Clock Generator
UBRRn [H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCKn
Transmitter
UDRn(Transmit) TX CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxDn
DATA BUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxDn
UDRn (Receive)
PARITY CHECKER
UCSRnA
UCSRnB
UCSRnC
Note:
1. P2Figure 1 P71Table40 USART0
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USART ( ) XCK ( ) USART UDRn
USART 4 USART UMSELn C (UCSRnC) ( ) UCSRnA U2X (UMSELn = 1) XCK (DDR_XCKn) ( ) ( ) XCKn Figure71 Figure 71.
UBRRn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 U2Xn
0 1 0 DDR_XCKn 1
OSC
txclk
xcki XCKn Pin xcko
Sync Register
Edge Detector
0 1
UMSELn
DDR_XCKn
UCPOLn
1 0
rxclk
txclk rxclk xcki xcko fosc -- ( ) ( ) XCK ( ) XCK ( ) XTAL ( )
Figure71 USARTUBRRn UBRRnL UBRRn fosc/(UBRRn+1) 2 8 16 2 8 16 UMSELn U2Xn DDR_XCKn
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Table73 (/)UBRRn Table 73.
(U2Xn = 0) (1) UBRRn
f OSC UBRRn = ----------------------- - 1 16BAUD f OSC BAUD = ------------------------------------------16 ( UBRRn + 1 )
(U2Xn = 1)
f OSC UBRRn = -------------------- - 1 8BAUD f OSC BAUD = --------------------------------------8 ( UBRRn + 1 )
f OSC UBRRn = -------------------- - 1 2BAUD f OSC BAUD = --------------------------------------2 ( UBRRn + 1 )
Note:
1. (bps)
BAUD ( bps) fOSC UBRRn UBRRnH UBRRnL (0-4095) Table81 UBRRn (U2Xn) UCSRnA U2Xn "0" U2Xn168 Figure71 XCKn CPU XCK f OSC f XCK < -----------4
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fosc
(UMSELn = 1) XCKn ( ) ( ) TxDn XCKn RxDn Figure 72. XCK
UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample
UCRSC UCPOLn XCKn Figure72 UCPOLn=0 XCKn XCKn UCPOLn=1
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure73 Figure 73.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
(0 8) (RxDn TxDn)
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ATmega48/88/168
UCSRnB UCSRnC UCSZn2:0 UPMn1:0 USBSn USART UCSZn2:0 UPMn1:0 USBSn (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
USART
USART USART ( ) USART TXCn RXC ( UDR )TXCn
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USART ( ) r17:r16 (1)
USART_Init: ; out out ldi out ldi out ret UBRRnH, r17 UBRRnL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRnH = (unsigned char)(baud>>8); UBRRnL = (unsigned char)baud; /* */ UCSRnB = (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O
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ATmega48/88/168
--USART
UCSRnB TXEN USART TxDn I/O USART XCKn CPU UDRn ( ) U2Xn XCKn UDREn 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRnA,UDREn rjmp USART_Transmit ; out ret UDRn,r16
5 8
C (1)
void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRnA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
UDREn
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9
9 (UCSZn = 7) 9 UCSRnB TXB8 8 UDRn 9 R17:R16 (1)(2)
USART_Transmit: ; sbis UCSRnA,UDREn rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRnB,TXB8 UCSRnB,TXB8 UDRn,r16 sbrc r17,0 ; 8
C (1)(2)
void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRnA & (1<Notes:
1. UCSRnB UCSRnB TXB8 2. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
9
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ATmega48/88/168
USART USART UDREn TXCn UDREn "1" UCSRnA "0" UCSRnB UDRIEn "1" UDREn ( ) USART UDRn UDREn UDRn UDREn TXCn TXCn "1" TXCn RS-485 UCSRB TXCIEn "1" TXCn USART TXCn TXCn (UPMn1 = 1) TXEN TxDn I/O
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--USART
UCSRB (RXENn) USART RxDn USART XCKn XCKn UDR RXCn 8 UDRn 0 USART (1)
USART_Receive: ; sbis UCSRnA, RXCn rjmp USART_Receive ; in ret r16, UDRn
5 8
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRnA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
RXCn
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ATmega48/88/168
9 9 (UCSZ=7) UDR 8 UCSRnB RXB8n 9 FEnDORn UPEn UCSRnA UDRn UDRn FIFO FIFO TXB8n FEn DORn UPEn USART 9 (1)
USART_Receive: ; sbis UCSRnA, RXCn rjmp USART_Receive ; 9 in in in r18, UCSRnA r17, UCSRnB r16, UDRn
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRnA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
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I/O USART (RXCn) 1 0( ) (RXENn = 0) RXCn UCSRB ((RXCIEn) RXCn ( ) USART UDRn RXCn USART (FEn) (DORn) (UPEn) UCSRnA UDRn UCSRnA (UDRn) "0" (FEn) ( 1) FEn 0 FE 1 UCSRnC USBSn FE UCSRnA 0 (DORn) ( ) DORn UDRn UDRn UCSRnA 0 DORn (UPEn) UPEn UCSRnA 0 P156" " P163" " UPMn1 ( ) UPMn0 (UPEn) (UPMn1 = 1) UPEn (UDRn) (RXENn ) RxDn FIFO
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ATmega48/88/168
FIFO UDRn RXCn (1)
USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
USART RxDn Figure74 16 8 (U2Xn = 1) RxDn ( ) 0 Figure 74.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8
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Figure75 Figure 75.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure76 Figure 76.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FEn Figure76 A B C ( Table74) ( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF D S SF SM (D = 5 10 ) S = 16 S = 8 SF = 8 SF = 4 SM = 9 SM = 5 ( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M
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ATmega48/88/168
Rslow Rfast Table74 Table75
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Table 74. (U2Xn = 0)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 93.20 94.12 94.81 95.36 95.81 96.17 Rfast (%) 106.67 105.79 105.11 104.58 104.14 103.78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5
Table 75. (U2Xn = 1)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104,35 103.90 103.53 103.23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRRn
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ATmega48/88/168
UCSRnA (MPCMn) USART CPU MPCMn 5 8 9 9 (RXB8n) ( 9 ) 1 MPCMn 9 (UCSZn = 7) (TXB8n = 1) 9 (TXB8n) 1 (TXBn = 0) 9 1. (UCSRnA MPCMn ) 2. UCSRnA RXCn 3. UDRn UCSRnA MPCMn MPCMn 1 4. MPCMn 1 5. MPCMn 2 5 8 n n+1 5 8 (USBSn = 1) - - (SBI CBI) MPCMn MPCMn TXCn I/O SBI CBI
USART
USART I/O --UDRn
7 6 5 4 RXB[7:0] TXB[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDRn ( ) UDRn ( )
USART USART I/O USART UDRn UDRn (TXB) UDRn (RXB) 567 0 UCSRnA UDREn UDREn UDRn USART
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TxDn FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO USART A-- UCSRnA
/ 7 RXCn R 0 6 TXCn R/W 0 5 UDREn R 1 4 FEn R 0 3 DORn R 0 2 UPEn R 0 1 U2Xn R/W 0 0 MPCMn R/W 0 UCSRnA
* 7 - RXCn: USART RXCn RXCn RXCn ( RXCIEn ) * 6 - TXCn: USART (UDRn) TXCn TXCn 1 TXCn ( TXCIEn ) * 5 - UDREn: USART UDREn (UDRn) UDREn 1 UDREn ( UDRIEn ) UDREn * 4 - FEn: 0 FEn (UDRn) 1 FEn "0" UCSRnA "0" * 3 - DORn: DORn ( ) (UDRn) UCSRnA "0" * 2 - UPEn: USART (UPMn1 = 1) UPEn (UDRn) UCSRnA "0" * 1 - U2Xn: 1 16 8
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ATmega48/88/168
* 0 - MPCMn: MPCMn USART MPCMn P168" " USART B-- UCSRnB
/ 7 RXCIEn R/W 0 6 TXCIEn R/W 0 5 UDRIEn R/W 0 4 RXENn R/W 0 3 TXENn R/W 0 2 UCSZn2 R/W 0 1 RXB8n R 0 0 TXB8n R/W 0 UCSRnB
* 7 - RXCIEn: RXCn RXCIEn 1 SREG UCSRn A RXCn 1 USART * 6 - TXCIEn: TXCn TXCIEn 1 SREG UCSRnA TXCn 1 USART * 5 - UDRIEn: USART UDREn UDRIEn 1 SREG UCSRnA UDREn 1 USART * 4 - RXENn: USART RxDn USART FEn DORn UPEn * 3 - TXENn: USART TxDn USART TXENn TxDn I/O * 2 - UCSZn2: UCSZn2 UCSRnC UCSZn1:0 ( ) * 1 - RXB8n: 8 9 RXB8n 9 UDRn RXB8n * 0 - TXB8n: 8 9 TXB8n9 UDRn
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USART nC-- UCSRnC
/
7 UMSELn1 R/W 0
6 UMSELn0 R/W 0
5 UPMn1 R/W 0
4 UPMn0 R/W 0
3 USBSn R/W 0
2 UCSZn1 R/W 1
1 UCSZn0 R/W 1
0 UCPOLn R/W 0 UCSRnC
* 7:6 - UMSELn1:0 USART USARTn Table76 . Table 76. UMSELn
UMSELn1 0 0 1 1 Note: UMSELn0 0 1 0 1 ( ) SPI (MSPIM)(1)
1. SPI (MSPIM) P177"SPI USART"
* 5:4 - UPMn1:0: UPMn UCSRnA UPEn Table 77. UPMn
UPMn1 0 0 1 1 UPMn0 0 1 0 1
* 3 - USBSn: Table 78. USBSn
USBSn 0 1 1 2
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ATmega48/88/168
* 2:1 - UCSZn1:0: UCSZn1:0 UCSRnB UCSZn2 ( ) Table 79. UCSZn
UCSZn2 0 0 0 0 1 1 1 1 UCSZn1 0 0 1 1 0 0 1 1 UCSZn0 0 1 0 1 0 1 0 1 5 6 7 8 9
* 0 - UCPOLn: UCPOLn XCKn Table 80. UCPOLn
UCPOLn 0 1 (TxDn ) XCKn XCKn (RxDn ) XCKn XCKn
USART --UBRRL UBRRH
15 - 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRnH UBRRnL 0 R/W R/W 0 0
UBRRn[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRRn[7:0] 4 R R/W 0 0 / R R/W 0 0
* 15:12 - * UBRRnH * 11:0 - UBRR11:0: USART 12 USART UBRRnH USART 4 UBRRnL 8 UBRRnL
Table81 UBRRn 0.5%
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( P165" " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 81. UBRRn
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k Note:
(1)
fosc = 1.8432 MHz U2Xn = 0
UBRRn
fosc = 2.0000 MHz U2Xn = 0
UBRRn
U2Xn = 0
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -
0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - -
0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0%
25 12 6 3 2 1 1 0 - - - -
51 25 12 8 6 3 2 1 1 0 - -
47 23 11 7 5 3 2 1 1 0 - -
95 47 23 15 11 7 5 3 2 1 0 -
51 25 12 8 6 3 2 1 1 0 - -
103 51 25 16 12 8 6 3 2 1 - 0
62.5 kbps
125 kbps
115.2 kbps
230.4 kbps
125 kbps
250 kbps
1. UBRRn = 0 = 0.0%
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Table 82. UBRRn ( )
fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2Xn = 1 U2Xn = 0
UBRRn
fosc = 7.3728 MHz U2Xn = 1 U2Xn = 0
UBRRn
U2Xn = 0
UBRRn
U2Xn = 1
UBRRn
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
UBRRn
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - -
UBRRn
0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
95 47 23 15 11 7 5 3 2 1 0 0 - -
191 95 47 31 23 15 11 7 5 3 1 1 0 -
103 51 25 16 12 8 6 3 2 1 0 0 - -
207 103 51 34 25 16 12 8 6 3 1 1 0 -
191 95 47 31 23 15 11 7 5 3 1 1 0 -
383 191 95 63 47 31 23 15 11 7 3 3 1 0
230.4 kbps UBRRn = 0 = 0.0%
460.8 kbps
250 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
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Table 83. UBRRn ( )
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2Xn = 0
UBRRn
fosc = 14.7456 MHz U2Xn = 0
UBRRn
U2Xn = 0
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
-0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0%
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
207 103 51 34 25 16 12 8 6 3 1 1 0 -
416 207 103 68 51 34 25 16 12 8 3 3 1 0
287 143 71 47 35 23 17 11 8 5 2 2 - -
575 287 143 95 71 47 35 23 17 11 5 5 2 -
383 191 95 63 47 31 23 15 11 7 3 3 1 0
767 383 191 127 95 63 47 31 23 15 7 6 3 1
0.5 Mbps UBRRn = 0 = 0.0%
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
174
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 84. UBRR ( )
fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 18.4320 MHz U2Xn = 0
UBRRn
fosc = 20.0000 MHz U2Xn = 0
UBRRn
U2Xn = 0
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
U2Xn = 1
UBRRn
-0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0%
0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0%
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% -
0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - -
0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
416 207 103 68 51 34 25 16 12 8 3 3 1 0
832 416 207 138 103 68 51 34 25 16 8 7 3 1
479 239 119 79 59 39 29 19 14 9 4 4 - -
959 479 239 159 119 79 59 39 29 19 9 8 4 -
520 259 129 86 64 42 32 21 15 10 4 4 - -
1041 520 259 173 129 86 64 42 32 21 10 9 4 -
1 Mbps UBRRn = 0 = 0.0%
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
175
2545A-AVR-09/03
SPI USART
USART SPI SPI (MSPIM) * , * * SPI ( 0, 1, 2 3) * LSB MSB( ) * ( ) * * (fXCKmax = fCK/2) * UMSELn1:0 "1" MSPIM USART SPI USART RX TX USART RX TX SPI I/O MSPIM
USART MSPIM ( ) MSPIM USART DDR_XCKn () MSPIMUSART( TXENn RXENn) DDR_XCKn MSPIM USART UBRRn Table85 Table 85.
(1) UBRRn
f OSC BAUD = --------------------------------------2 ( UBRRn + 1 )
f OSC UBRRn = -------------------- - 1 2BAUD
Note:
1. (bps)
BAUD ( bps) fOSC UBRRn UBRRnH UBRRnL (0-4095)
SPI
XCKn (SCK) UCPHAn UCPOLn Figure77 XCKn
176
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
UCPOLn UCPHAn Table86 Table 86. UCPOLn UCPHAn
UCPOLn 0 0 1 1 UCPHAn 0 1 0 1 SPI 0 1 2 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
Figure 77. UCPHAn UCPOLn
UCPOL=0
UCPHA=1
XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD)
UCPOL=1
UCPHA=0
XCK Data setup (TXD) Data sample (RXD)
XCK Data setup (TXD) Data sample (RXD)
MSPIM 8 MSPIM USART * * 8 MSB 8 LSB
8 MSPIM USART UCSRnC UDORDn UDRn 16 UART 16 USART MSPIM
USART USART ()
Note: XCKn (UBRRn) "0" USART UBRRn UBRRn UBRRn UBRRn "0"
USART TXCn RXCn ( UDR )TXCn
177
2545A-AVR-09/03
USART ( ) r17:r16 (1)
USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; XCKn sbi XCKn_DDR, XCKn ; MSPI SPI 0 ldi r18, (1<C (1)
void USART_Init( unsigned int baud ) { UBRRn = 0; /* XCKn */ XCKn_DDR |= (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
MSPI USART UCSRnB TXENn "1" TxDn UCSRnB RXENn "1" RxDn XCKn USART UDRn UDRn
Note: UDRn USART
178
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
4 1 2 34 UDRn 3 1
MSPI USART UDRE (RXCn) USART R16 UDREn RXCn . (1)
USART_MSPIM_Transfer: ; sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; out UDRn,r16 ; USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; in r16, UDRn ret
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !( UCSRnA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
MSPIM USART USART RXCn TXCn UDREn MSPIM (FEDOR PE) "0" MSPIM USART USART
179
2545A-AVR-09/03
USART MSPIM
USART MSPIM I/O --UDRn USART MSPIM A--UCSRnA
MSPIM USART
MSPIM USART USART UDRn P168 "USART I/O - UDRn"
*
/
7 RXCn R/W 0
6 TXCn R/W 0
5 UDREn R/W 0
4 R 0
3 R 0
2 R 1
1 R 1
0 R 0 UCSRnA
* 7 - RXCn: USART RXCn RXCn RXCn ( RXCIEn ) * 6 - TXCn: USART (UDRn) TXCn TXCn "1" TXCn ( TXCIEn ) * 5 - UDREn: USART UDREn(UDRn) UDREn"1" UDREn ( UDRIEn ) UDREn * 4:0 - MSPI MSPI UCSRnA "0" USART MSPIM B--UCSRnB
/
7 RXCIEn R/W 0
6 TXCIEn R/W 0
5 UDRIE R/W 0
4 RXENn R/W 0
3 TXENn R/W 0
2 R 1
1 R 1
0 R 0 UCSRnB
* 7 - RXCIEn: RX RXCIEn RXCn RXCIEn "1" SREG "1" UCSRnA RXCn "1" USART * 6 - TXCIEn: TX TXCIEnTXCn TXCIEn"1" SREG"1" UCSRnA TXCn "1" USART * 5 - UDRIE: USART UDRIEUDREn UDRIE"1" SREG"1" UCSRnA UDREn "1" USART
180
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* 4 - RXENn: RXENnMSPIMUSART RxDn MSPIM ( RXENn=1TXENn=0) MSPIM * 3 - TXENn: TXENnUSART TxDn ( TXENn=0) TxDn * 2:0 - MSPI MSPI UCSRnB "0" USART MSPIM C--UCSRnC
/ 7 UMSELn1 R/W 0 6 UMSELn0 R/W 0 5 R 0 4 R 0 3 R 0 2 UDORDn R/W 1 1 UCPHAn R/W 1 0 UCPOLn R/W 0 UCSRnC
* 7:6 - UMSELn1:0: USART USART Table87.P171"USART n C - UCSRnC" USART "1" MSPIM MSPIM UDORDn UCPHAn UCPOLn Table 87. UMSELn
UMSELn1 0 0 1 1 UMSELn0 0 1 0 1 USART USART ( ) SPI (MSPIM)
* 5:3 - MSPI MSPI UCSRnC "0" * 2 - UDORDn: UDORDn "1" LSB MSB * 1 - UCPHAn: UCPHAn XCKn SPI * 0 - UCPOLn: UCPOLn XCKn UCPOLn UCPHAn SPI
181
2545A-AVR-09/03
USART MSPIM -- UBRRnL UBRRnH
MSPI USART P172 "USART -UBRRL UBRRH" MSPIM USART AVR SPI * * * * UCPOLn SPI CPOL UCPHAn SPI CPHA UDORDn SPI DORD
AVR USART MSPIM AVR SPI
MSPIM USART USART MSPIM USART SPI MSPIM USART * * * * * * MSPIM USART SPI MSPIM USART MSPIM USART SPI WCOL ( ) MSPIM USART SPI (SPI2X) UBRRn MSPIM USART
MSPIM USART SPI P182Table88 Table 88. MSPIM USART SPI
USART_MSPIM TxDn RxDn XCKn (N/A) SPI MOSI MISO SCK SS ( ) MSPIM USART
182
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* * * * * * * * * *
/ 7 128 400 kHz AVR
(TWI) TWI ( SCL SDA) 128 Figure 78. TWI
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI
Table 89. TWI
Master Slave Transmitter Receiver SCL
183
2545A-AVR-09/03
Figure78 TWI TWI "0" TWI TWI TWI AVR 400 pF 7 TWI P280"SPI " 100 kHz 400 kHz
TWI Figure 79.
SDA
SCL Data Stable Data Stable
Data Change
START STOP START STOP START STOP START STOP START REPEATED START REPEATED START STOP START START REPEATED START START START STOP SCL SDA Figure 80. START REPEATED START STOP
SDA
SCL
START
STOP
START
REPEATED START
STOP
184
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI 9 7 1 READ/WRITE 1 READ/WRITE 1 SCL (ACK) SDA ACK SDA STOP REPEATED START SLA+R SLA+W READ WRITE MSB 0000 000 ACK SDA Write ACK SDA Read 1111 xxx Figure 81.
Addr MSB SDA Addr LSB R/W ACK
SCL 1 START 2 7 8 9
TWI 9 8 1 START STOP 9 SCL SDA SDA NACK NACK MSB Figure 82.
Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 SLA+R/W 2 7 Data Byte 8 9 STOP, REPEATED START or Next Data Byte Data LSB ACK
START SLA+R/W STOP START STOP SCL SCL SCL SCL SCL SCL SCL TWI 185
2545A-AVR-09/03
Figure83 SLA+R/W STOP Figure 83.
Addr MSB SDA
Addr LSB
R/W
ACK
Data MSB
Data LSB
ACK
SCL 1 START 2 7 SLA+R/W 8 9 1 2 Data Byte 7 8 9 STOP
186
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI
*
*
SCL
SCL / SCL / Figure 84. SCL
TA low
TA high
SCL from Master A
SCL from Master B
SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period
SDA SDA SDA SDA
187
2545A-AVR-09/03
Figure 85.
START SDA from Master A Master A Loses Arbitration, SDAA SDA
SDA from Master B
SDA Line
Synchronized SCL Line
* * * REPEATED START STOP REPEATED START STOP
SLA+R/W
188
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI
TWI Figure86 AVR Figure 86. TWI
SCL
Slew-rate Control Spike Filter
SDA
Slew-rate Control Spike Filter
Bus Interface Unit
START / STOP Control Spike Suppression
Bit Rate Generator
Prescaler
Arbitration detection
Address/Data Shift Register (TWDR)
Ack
Bit Rate Register (TWBR)
Address Match Unit
Address Register (TWAR)
Control Unit
Status Register (TWSR) Control Register (TWCR)
Address Comparator
State Machine and Status control
SCL SDA
SCL SDAMCU TWI TWI 50 ns SCL SDA I/O
TWI Unit
189
2545A-AVR-09/03
TWI SCL TWI TWSR TWBR TWI CPU TWI SCL 16 SCL TWI SCL CPU Clock frequency SCL frequency = -----------------------------------------------------------TWPS 16 + 2(TWBR) 4 * * TWBR = TWI TWPS = TWI
TWI TWBR 10 SDA SCL TWI Start + SLA + R/W ( )
Note:
TWDRSTART/STOP TWDR 8 TWDR (N)ACK (N)ACK TWI TWCR (N)ACK TWCR START/STOP TWI START REPEATED START STOP MCU START/STOP TWI START/STOP TWI MCU TWI TWI
TWAR 7 TWAR TWI TWGCE "1" TWI TWCR MCU MCU TWI MCU TWI TWI TWI TWI TWCR TWI TWI TWINT TWI TWSR TWSR TWINT "1" SCL TWI TWINT * * * * * * * TWI START/REPEATED START TWI SLA+R/W TWI TWI TWI ( ) TWI TWI STOP REPEATED START
190
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* START STOP
TWI
TWI --TWBR
/ 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR
* 7..0 - TWI TWBR SCL P191" " TWI --TWCR
/ 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR
TWCR TWI TWI START STOP TWDR TWDR TWDR * 7 - TWINT: TWI TWI TWINT SREG I TWCR TWIE MCU TWI TWINT SCL TWINT "1" "0" TWI TWINT TWAR TWSR TWDR * 6 - TWEA: TWI TWEA TWEA ACK 1. 2. TWAR TWGCE 3. / TWEA * 5 - TWSTA: TWI START CPU TWSTA TWI START STOP START START TWSTA * 4 - TWSTO: TWI STOP TWSTOTWI STOP TWSTO TWSTO
191
2545A-AVR-09/03
STOP TWI SCL SDA * 3 - TWWC: TWI TWINT TWDR TWWC TWDR * 2 - TWEN: TWI TWEN TWITWI TWEN"1" TWII/O SCL SDA TWI TWI * 1 - Res: * "0" * 0 - TWIE: TWI SREG I TWIE TWINT "1" TWI
192
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI --TWSR
/ 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 TWPS1 R/W 0 0 TWPS0 R/W 0 TWSR
* 7..3 - TWS: TWI 5 TWI TWSR 5 2 "0" * 2 - Res: "0" * 1..0 - TWPS: TWI / Table 90. TWI
TWPS1 0 0 1 1 TWPS0 0 1 0 1 1 4 16 64
P191" " TWPS1..0 TWI --TWDR
/ 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR
TWDR TWDR TWI (TWINT ) TWINT TWDR TWDR MCU TWI TWDR ACK TWI CPU ACK * 7..0 - TWD: TWI TWI --TWAR
/ 7
TWA6
6
TWA5
5
TWA4
4
TWA3
3
TWA2
2
TWA1
1
TWA0
0
TWGCE TWAR
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 0
193
2545A-AVR-09/03
TWAR 7 TWI TWAR TWAR LSB (0x00) * 7..1 - TWA: TWI * 0 - TWGCE: TWI MCU TWI TWI -- TWAMR
/
7 R/W 0
6 R/W 0
5 R/W 0
4
TWAM[6:0]
3 R/W 0
2 R/W 0
1 R/W 0
0
- TWAMR
R/W 0
R 0
* 7..1 - TWAM: TWI TWAMR 7 TWAMR TWI TWAR "1" TWAR Figure87 Figure 87. TWI
TWAR0 Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Match
Address Bit Comparator 6..1
* 0 - Res: ATmega48/88/168 "0"
TWI
AVR TWI START TWI TWI TWI TWCR TWI TWIESREGTWINT TWIE TWINT TWI TWINT "1" TWI TWI TWSR TWI TWCR TWCR TWDR TWI TWI
194
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure88 TWI Figure 88. TWI
Application Action 1. Application writes to TWCR to initiate transmission of START 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. 5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
TWI bus
START
SLA+W
A
Data
A
STOP
2. TWINT set. Status code indicates START condition sent
4. TWINT set. Status code indicates SLA+W sent, ACK received
TWI Hardware Action
6. TWINT set. Status code indicates data sent, ACK received
Indicates TWINT set
1. TWI START TWCR TWI START TWINT TWINT "1" TWCR TWINT TWI TWINT TWI START 2. START TWCR TWINT TWCR START 3. TWSR START TWSR SLA+W TWDR TWDR TWDR SLA+W TWCR TWI SLA+W TWINT TWINT "1" TWCR TWINT TWI TWINT TWI 4. TWCR TWINT TWDR 5. TWSRACK TWSR TWDR TWCR TWI TWDR TWINT TWCR TWINT TWI TWINT TWI 6. TWCR TWINT TWSR 7. TWSR ACK TWSR TWCR TWI STOP TWINT TWINT "1" TWCR TWINT TWI TWINT TWI STOP TWINT STOP 195
2545A-AVR-09/03
TWI * * * TWI TWINT TWINT SCL TWINT TWI TWI TWDR TWI TWCR TWCR TWINT TWINT "1" TWI TWCR
C
1
ldi out r16, (1<C
TWCR = (1< START
2
wait1: in sbrs r16,TWINT rjmp wait1
TWINT TWINT START
3
in cpi ldi out ldi out
r16,TWSR r16, START r16, SLA_W TWDR, r16 r16, (1<if ((TWSR & 0xF8) != START) ERROR();
andi r16, 0xF8 brne ERROR
TWI START SLA_W TWDR TWINT
TWDR = SLA_W; TWCR = (1<4
wait2: in r16,TWCR sbrs r16,TWINT rjmp wait2
while (!(TWCR & (1< TWINT TWINT SLA+W ACK/NACK TWI MT_SLA_ACK TWDR TWINT
5
in cpi ldi out ldi out
r16,TWSR r16, MT_SLA_ACK r16, DATA TWDR, r16 r16, (1<if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR();
andi r16, 0xF8 brne ERROR
TWDR = DATA; TWCR = (1<6
wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3
while (!(TWCR & (1< TWINT TWINT DATA ACK/NACK TWI MT_DATA_ACK STOP
7
in cpi ldi out
r16,TWSR r16, MT_DATA_ACK r16, (1<if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();
andi r16, 0xF8 brne ERROR
TWCR = (1<196
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI 4 (MT) (MR) (ST) (SR) TWI MT TWI EEPROM MR EEPROM TWI SR S START RsREPEATED START R (SDA ) W (SDA ) A (SDA ) A (SDA ) Data8 P STOP SLA Figure90 Figure96 TWINT TWSR 0 / TWI TWI TWINT TWINT TWSRTable91 Table94 0
197
2545A-AVR-09/03
Figure89 START MT MR SLA+W MT SLA+R MR "0" Figure 89.
VCC
Device 1
MASTER TRANSMITTER
Device 2
SLAVE RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN 2 TWSTA"1" START TWINT "1" TWINT TWI START TWINT TWSR0x08 ( Table91)MT SLA+W TWDR SLA+W TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+W TWINT TWSR 0x18 0x20 0x38 Table91 SLA+W TWDR TWDR TWINT TWCR TWWC TWDR TWINT TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR value TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
198
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
REPEATED START ( 0x10) 2 STOP REPEATED START Table 91.
(TWSR) "0"
0x08
TWCR 2 2 START START / TWDR SLA+W SLA+W SLA+R STA
0
STO
0
TWIN T
1
TWE A
X
2 SLA+W ACK NOT ACK SLA+W ACK NOT ACK SLA+R
0x10
0 0
0 0
1 1
X X
0x18
SLA+W ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
0x20
SLA+W NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
0x28
ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
0x30
NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
0x38
SLA+W
TWDR TWDR
0 1
0 0
1 1
X X
2 START
199
2545A-AVR-09/03
Figure 90.
MT
Successfull transmission to a slave receiver
S
SLA
W
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$18
$28
RS
SLA
W
$10
Not acknowledge received after the slave address
A
P
R
$20
MR
Not acknowledge received after a data byte
A
P
$30
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
200
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure91 START MT MR SLA+W MT SLA+R MR "0" Figure 91.
VCC
Device 1
MASTER RECEIVER
Device 2
SLAVE TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN 2 TWSTA"1" START TWINT "1" TWINT TWI START TWINT TWSR 0x08 ( Table91) MR SLA+R TWDR SLA+R TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+R TWINT TWSR 0x38 0x40 0x48 Table92 TWDR TWINT MR NACK STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( 0x10) 2 STOP REPEATED START Table 92.
(TWSR) "0" TWCR 2 2 / TWDR STA STO TWIN T TWE A 2
201
2545A-AVR-09/03
Table 92.
0x08
START START
SLA+R SLA+R SLA+W
0
0
1
X
SLA+R ACK NOT ACK SLA+R ACK NOT ACK SLA+W
0x10
0 0
0 0
1 1
X X
0x38
SLA+R NOT ACK SLA+R ACK SLA+R NOT ACK
TWDR TWDR
0 1
0 0 0 0 0 1 1
1 1 1 1 1 1 1
X X 0 1
2 START NOT ACK ACK
0x40
TWDR TWDR
0 0
0x48
TWDR TWDR TWDR
1 0 1
X X X
START STOP TWSTO STOP START TWSTO
0x50
ACK NOT ACK

0 0
0 0 0 1 1
1 1 1 1 1
0 1
NOT ACK ACK
0x58

1 0 1
X X X
START STOP TWSTO STOP START TWSTO
202
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 92.
MR
Successfull reception from a slave receiver
S
SLA
R
A
DATA
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$40
$50
$58
RS
SLA
R
$10
Not acknowledge received after the slave address
A
P
W
$48
MT
Arbitration lost in slave address or data byte
A or A
Other master continues
A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Figure93 "0" Figure 93.
VCC
Device 1
SLAVE RECEIVER
Device 2
MASTER TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
203
2545A-AVR-09/03
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) 0 ( ) TWINT TWSR Table93 TWI ( 0x68 0x78) CPU TWEA TWI SDA " " TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVRTWI AVR SCL MCU TWDR
204
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 93.
(TWSR) "0"
0x60
TWCR 22 SLA+W ACK SLA+R/W SLA+W ACK ACK SLA+R/W ACK SLA+W ACK SLA+W NOT ACK / TWDR TWDR TWDR STA
X X
STO
0 0 0 0
TWIN T
1 1 1 1
TWE A
0 1
2 NOT ACK ACK
0x68
TWDR TWDR TWDR TWDR
X X
0 1
NOT ACK ACK
0x70
X X
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1
NOT ACK ACK
0x78
TWDR TWDR TWDR TWDR
X X X X 0 0 1
0 1
NOT ACK ACK
0x80
0 1
NOT ACK ACK
0x88
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
205
2545A-AVR-09/03
Table 93.
0x90
ACK NOT ACK
r
X X 0 0 1
0 0 0 0 0
1 1 1 1 1
0 1
NOT ACK ACK
0x98
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
0xA0
STOP START
r
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
1 0 1 1
206
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 94.
Reception of the own slave address and one or more data bytes. All are acknowledged
S
SLA
W
A
DATA
A
DATA
A
P or S
$60
Last data byte received is not acknowledged
$80
$80
$A0
A
P or S
$88
Arbitration lost as master and addressed as slave
A
$68
Reception of the general call address and one or more data bytes
General Call
A
DATA
A
DATA
A
P or S
$70
Last data byte received is not acknowledged
$90
$90
$A0
A
P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
207
2545A-AVR-09/03
Figure95 "0" Figure 95.
VCC
Device 1
SLAVE TRANSMITTER
Device 2
MASTER RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) "1" ( ) TWI TWSR Table94 TWI ( 0xB0) CPU TWEA TWI 0xC0 0xC8 "1" ( ACK) 0xC8 TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVR AVR SCL MCU TWDR
208
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 94.
(TWSR) "0"
0xA8
TWCR 22 SLA+R ACK / TWDR STA
X X
STO
0 0
TWIN T
1 1
TWE A
0 1
2 NOT ACK ACK
0xB0
SLA+R/W SLA+R ACK TWDR ACK

X X
0 0
1 1
0 1
NOT ACK ACK
0xB8
X X
0 0
1 1
0 1
NOT ACK ACK
0xC0
TWDR NOT ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
TWDR
1 0 1 1
TWDR
0xC8
TWDR (TWAE = "0"); ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA GC = "1" GCA SLA GCA START SLA GC = "1" GCA START
TWDR
1 0 1 1
TWDR
209
2545A-AVR-09/03
Figure 96.
Reception of the own slave address and one or more data bytes
S
SLA
R
A
DATA
A
DATA
A
P or S
$A8
Arbitration lost as master and addressed as slave
$B8
$C0
A
$B0
Last data byte transmitted. Switched to not addressed slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
TWI Table95 0xF8 TWINT "0" TWI 0x00 START STOP ACKSTARTSTOP TWINT TWSTO "1" TWINT TWI TWSTO (TWCR ) SDA SCL STOP
Table 95.
(TWSR) "0"
0xF8
TWCR 2 2 TWINT = "0" START STOP / TWDR TWDR TWDR
0
STA
STO
TWIN T
TWE A
2
No TWCR action
0x00
1
1
X
STOP TWSTO
210
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
TWI TWI EEPROM 1. 2. EEPROM 3. 4. MT MR EEPROM REPEATED START REPEATED START Figure 97. TWI EEPROM
Master Transmitter Master Receiver
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
S = START Transmitted from master to slave
Rs = REPEATED START Transmitted from slave to master
P = STOP
TWI Figure 98.
VCC
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
........
Device n
R1
R2
SDA
SCL
* * READ/WRITE SDA "0" START
211
2545A-AVR-09/03
*
SLA SDA "0" SLA SR ST SLA READ/WRITE START
Figure99 TWI Figure 99.
START SLA Data STOP
Arbitration lost in SLA
Arbitration lost in Data
Own Address / General Call received
No
38
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
Yes Write 68/78
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Direction
Read B0
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
212
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure100 Figure 100. (2)
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT (1)
Notes:
1. P215Table97 2. P2Figure 1 P71Table40
ADC B-- ADCSRB
/
7 - R 0
6 ACME R/W 0
5 - R 0
4 - R 0
3 - R 0
2 ADTS2 R/W 0
1 ADTS1 R/W 0
0 ADTS0 R/W 0 ADCSRB
* 6 - ACME: "1" ADC (ADCSRA ADEN "0") ADC "0" AIN1 P216" " -- ACSR
7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR
* 7 - ACD: ACD ACD ACSR ACIE ACD * 6 - ACBG: ACBG AIN0 P43" "
213
2545A-AVR-09/03
* 5 - ACO: ACO 1-2 * 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI "1" * 3 - ACIE: ACIE "1" I * 2 - ACIC: ACIC T/C1 T/C1 ACIC "0" T/C1 TIMSK1 ICIE1 * 1, 0 - ACIS1, ACIS0: Table96 Table 96. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR
214
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ADC7..0 ADC ADC (ADCSRB ACME) ADC (ADCSRA ADEN 0) ADMUX MUX2..0 Table97 ACME ADEN AIN1 Table 97.
ACME 0 1 1 1 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
1--DIDR1
/
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 AIN1D R/W 0
0 AIN0D R/W 0 DIDR1
* 7..2 - Res: ATmega48/88/168 "0" * 1, 0 - AIN1D, AIN0D: AIN1, AIN0 AIN1DAIN0D"1" AIN1/0 PIN "0" AIN1/0 AIN1/0 AIN1D AIN0D
215
2545A-AVR-09/03
* * * * * * * * * * * * *
10 0.5 LSB 2 LSB 65 - 260 s 15 kSPS 6 2 (TQFP MLF ) ADC 0 - VCC ADC 1.1V ADC ADC
ATmega48/88/168 10 ADC ADC 8 A 8 0V (GND) ADC ADC ADC Figure101 ADC AVCC AVCC VCC 0.3V P223"ADC " 1.1V AVCC AREF
216
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 101.
ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
MUX2 MUX3 MUX1 REFS0 ADLAR REFS1 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADPS2 ADPS1
ADSC
ADEN
ADFR
MUX DECODER PRESCALER
CHANNEL SELECTION
ADIF
CONVERSION LOGIC
AVCC
INTERNAL 1.1V REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
GND
BANDGAP REFERENCE
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
INPUT MUX
ADC MULTIPLEXER OUTPUT
ADC 10 GND AREF 1 LSB ADMUX REFSn AVCC 1.1V AREF AREF ADMUX MUX ADC GND ADC ADCSRA ADEN ADC ADEN ADEN ADC ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL
217
2545A-AVR-09/03
ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC
ADC ADSC "1" ADC ADC ADCSRAADCADATE ADCSRB ADC ADTS ( ADTS ) ADC 0 Figure 102. ADC
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
ADC ADC ADC ADC ADCSRA ADSC 1 ADC ADC ADIF ADCSRA ADSC ADSC ADSC "1"
218
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ADC
Figure 103. ADC
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz 10 200 kHz ADC 100 kHz CPU ADC ADCSRA ADPS ADCSRA ADEN ADC ADEN 1 ADEN ADCSRA ADSC ADC 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC 2 ADC 3 CPU ADSC 1 Table98
CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
219
2545A-AVR-09/03
Figure 104. ADC ( )
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
Figure 105. ADC
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
Figure 106. ADC
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
220
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 107. ADC
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
Sign and MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 98. ADC
& ( ) 14.5 1.5 2 ( ) 25 13 13.5
221
2545A-AVR-09/03
ADMUXMUXnREFS1:0 CPU ADC (ADCSRA ADIF ) ADSC ADSC ADC ADMUX ADMUX ADATE ADEN ADMUX ADMUX 1. ADATE ADEN "0" 2. ADC 3. ADMUX ADC
ADC
ADSC ADC ADSC ADC
ADC
ADC(VREF)ADC VREF 0x3FF VREF AVCC 1.1V AREF AVCC ADC 1.1V(VBG) AREF ADC AREF VREF AREF VREF AREF AREF AVCC 1.1V ADC
ADC
ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC 3. ADC ADCCPU ADC ADC CPU ADC ADC CPU
222
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ADC ADC ADEN Figure 108. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H (fADC/2) ADC Figure 108.
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
(EMI) 1. 2. Figure109 AVCC LC VCC 3. ADC CPU 4. ADC[3..0] TWI (ADC4 ADC5) ADC4 ADC5 ADC
223
2545A-AVR-09/03
Figure 109. ADC
PC4 (ADC4/SDA) PC5 (ADC5/SCL)
PC1 (ADC1)
PC0 (ADC0) ADC7 GND AREF ADC6 AVCC
PB5
ADC
n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB
Figure 110.
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
224
ATmega48/88/168
2545A-AVR-09/03
100nF
10H
Analog Ground Plane
PC3 (ADC3)
GND
VCC
PC2 (ADC2)
ATmega48/88/168
* (0x3FE 0x3FF) ( 1.5 LSB) 0 LSB
Figure 111.
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
*
(INL) INL0 LSB
Figure 112. (INL)
Output Code
*
(DNL) ( ) (1 LSB) 0 LSB
INL
Ideal ADC Actual ADC VREF Input Voltage
225
2545A-AVR-09/03
Figure 113. (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* *
(1 LSB) 0.5 LSB ( ) 0.5 LSB
ADC
(ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF V IN V REF ( P226Table99 P227Table100 ). 0x000 0x3FF 1LSB
ADC -- ADMUX
/
7 REFS1 R/W 0
6 REFS0 R/W 0
5 ADLAR R/W 0
4 - R 0
3 MUX3 R/W 0
2 MUX2 R/W 0
1 MUX1 R/W 0
0 MUX0 R/W 0 ADMUX
* 7:6 - REFS1:0: Table99 (ADCSRA ADIF ) AREF Table 99. ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 AREF Vref AVCC AREF 1.1V AREF
226
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* 5 - ADLAR: ADC
ADLARADCADC ADLAR ADLAR ADC P229"ADC - ADCL ADCH" * 4 - Res: ATmega48/88/168 "0" * 3:0 - MUX3:0: ADC Table100 (ADCSRA ADIF ) Table 100.
MUX3..0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ( ) ( ) ( ) ( ) ( ) ( ) 1.1V (VBG) 0V (GND)
ADC A-- ADCSRA

7 ADEN R/W 0
6 ADSC R/W 0
5 ADATE R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* 7 - ADEN: ADC ADENADC ADC ADC
227
2545A-AVR-09/03
* 6 - ADSC: ADC ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC "1"ADSC * 5 - ADATE: ADC ADATE ADC ADC ADCSRB ADC ADTS * 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * 3 - ADIE: ADC ADIE SREG I ADC * 2:0 - ADPS2:0: ADC XTAL ADC Table 101. ADC
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128
ADC --ADCL ADCH ADLAR = 0
15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
228
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ADLAR = 1
15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
ADC ADCL ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P227"ADC "
229
2545A-AVR-09/03
ADC B-- ADCSRB

7 - R 0
6 ACME R/W 0
5 - R 0
4 - R 0
3 - R 0
2 ADTS2 R/W 0
1 ADTS1 R/W 0
0 ADTS0 R/W 0 ADCSRB
* 7, 5:3 - Res: ADCSRB "0" * 2:0 - ADTS2:0: ADC ADCSRA ADATE ADTS ADC ADTS ADC ADCSRA ADEN 1 ADC (ADTS[2:0]=0) ADC Table 102. ADC
ADTS2 0 0 0 0 1 1 1 1 ADTS1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 0 / 0 / 0 / B / 1 / 1
0--DIDR0
/ e
7 - R 0
6 - R 0
5 ADC5D R/W 0
4 ADC4D R/W 0
3 ADC3D R/W 0
2 ADC2D R/W 0
1 ADC1D R/W 0
0 ADC0D R/W 0 DIDR0
* 7:6 - Res: DIDR0 "0" * 5..0 - ADC5D..ADC0D: ADC5..0 "1" ADC PIN "0" ADC5..0 "1" ADC ADC7 ADC6
230
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
* * * * * * * * * *
RESET (C HLL) ( )

debugWIRE CPU AVR debugWIRE DWEN debugWIRE RESET ( ) I/O Figure 114. debugWIRE
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure114 debugWIRE MCU debugWIRE CKSEL debugWIRE * * * * dW/(RESET) 10k debugWIRE RESET VCC debugWIRE RESET
debugWIRE AVR AVR Studio(R) BREAK BREAK
231
2545A-AVR-09/03
BREAK Flash AVR Studio(R) debugWIRE Flash
debugWIRE
debugWIRE (dW) (RESET) debugWIRE CPU debugWIRE I/O CPU I/O debugWIRE DWEN debugWire DWEN
I/O debugWIRE
debugWire --DWDR
debugWire
/
7 R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 DWDR R/W 0
DWDR[7:0]
DWDR MCU debugWIRE
232
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Flash ATmega48
ATmega48 (R-W-W) Boot Loader SPM Flash MCU ( ) SPM 1 * * * * * *
2
( ) 1 Boot Loader - - 2 SPM Z "00000011" SPMCSR SPMR1 R0 Z PCPAGE Z * ( ) CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE SPM EEPROM
Z "00000101" SPMCSR SPMR1 R0 Z PCPAGE Z * CPU
Flash
Z SPM
ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash (P261Table126 ) Figure118 Boot Loader
233
2545A-AVR-09/03
LPMZ ZLSB ( Z0) Figure 115. SPM(1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. Figure118 P261Table126
234
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
(SPM) SPMCSR Boot Loader --SPMCSR
7 6 5
-
4
3
2
PGWRT
1
PGERS
0
SPMEN SPMCSR
SPMIE
RWWSB
RWWSRE
BLBSET
/
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7 - SPMIE: SPM SPMIE I SPM SPMCSR SPMEN SPM * 6 - RWWSB:RWW RWWSB RWW ATmega48 "0" * 5 - Res: ATmega48/88/168 "0" * 4 - RWWSRE: RWW ATmega48 ATmega88/168 RWWSRE * 3 - BLBSET: Boot ATmega48 ATmega88/168 SPMCSR BLBSET SPMEN LPM ( Z Z0) P237" " * 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN "10001" "01001" "00101" "00011" "00001"
235
2545A-AVR-09/03
EEPROM SPMCSR
EEPROM Flash SPMCSR EECR EEWE 0x0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 LB2 0 LB1
0x0000ZSPMCSRBLBSET SPMEN SPMCSR CPU LPM (FLB) P256Table119
Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (FHB) P256Table118 SPMCSR CPU LPM
Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
(EFB) P256Table119
Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
/ "0" / "1" Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( ) 1. AVR RESET BOD 2. AVR CPU SPMCSR Flash
236
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
SPM Flash RC Flash Table108 CPU Flash Table 103. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
237
2545A-AVR-09/03
Boot Loader
ATmega48 RWWSB "0" RWW
;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi rcall ; ldi rcall ; ldi ldi Wrloop: ld ld ldi rcall adiw sbiw brne ; r0, Y+ r1, Y+ spmcrval, (1< RWW spmcrval, (1< RAM Flash looplo, low(PAGESIZEB) loophi, high(PAGESIZEB) ; ;PAGESIZEB<=256
ZL, low(PAGESIZEB) ZH, high(PAGESIZEB) spmcrval, (1<subi sbci ldi rcall ; ldi rcall ; ldi ldi
RWW spmcrval, (1< looplo, low(PAGESIZEB) loophi, high(PAGESIZEB) ; ;PAGESIZEB<=256
238
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
subi sbci Rdloop: lpm ld cpse rjmp sbiw brne ; ; in sbrs ret ; ldi rcall rjmp Do_spm: ; in sbrc rjmp ; ; in cli ; EEPROM EECR, EEPE Wait_ee SPMCSR, spmcrval SREG ( ) SREG, temp2 Wait_ee: sbic rjmp ; out spm ; out ret SPM temp1, SPMCSR temp1, SPMEN Wait_spm spmcrval SPM temp2, SREG Wait_spm: RWW spmcrval, (1< RWW RWW temp1, SPMCSR temp1, RWWSB ; RWWSB"1" RWW
Return:
SPM
239
2545A-AVR-09/03
Boot Loader RWW ATmega88 ATmega168
ATmega88 ATmega168 Boot Loader MCU - (Read-While-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Flash Boot Loader Flash Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * *
RWW Boot Loader ( Boot ) (1) RWW 1. Flash (P261Table126 )
Boot Loader
Note:
Flash Boot Loader Flash
Flash Boot Loader ( Figure117) BOOTSZ P252Table109 Figure117 Flash Boot (Boot 0) P243Table105 SPM Boot Loader Boot Loader BLS BLS SPM SPM Flash BLS Boot Loader Boot Loader (Boot 1) P243Table106 CPU RWW CPU Boot Loader BOOTSZ Flash ---- - (RWW) - (NRWW) RWW NRWW P252Table110 P242Figure 117 * * RWW NRWW NRWW CPU
BLS--Boot Loader
RWW RWW Flash
Boot Loader RWW "RWW " ( ) Boot Loader RWW---- Boot Loader RWW Flash NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSB P244" - SPMCSR"
240
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
NRWW---- Boot Loader RWW NRWW Boot Loader NRWW CPU Table 104. RWW
Z ? RWW NRWW ? NRWW CPU ? RWW ?
Figure 116. RWW NRWW
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation
241
2545A-AVR-09/03
Figure 117.
Program Memory BOOTSZ = '11' 0x0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' 0x0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' 0x0000
Read-While-Write Section Read-While-Write Section
0x0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. P252Table109
Boot Loader
Boot Loader Flash Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU Flash
Table105 Table106 Boot ( 2) SPM Flash / ( 1) LPM/SPM /
242
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 105. Boot
BLB0 1 2 3
0 ( )(1)
BLB01 1 0 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader 1 1 0
BLB02
4
0
1
Note:
1. "1" "0"
Table 106. Boot
BLB1 1 2 3
1 (Boot Loader )(1)
BLB11 1 0 0 SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader 1 1 0
BLB12
4
0
1
Note:
1. "1" "0"
Boot Loader
Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot Table 107. Boot (1)
BOOTRST 1 0 Note: = ( 0x0000) =Boot Loader ( P252Table109 )
1. "1" , "0"
--SPMCSR
Boot Loader
/ 7
SPMIE
6
RWWSB
5
-
4
RWWSRE
3
BLBSET
2
PGWRT
1
PGERS
0
SPMEN SPMCSR
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
243
2545A-AVR-09/03
* 7 - SPMIE: SPM SPMIE I SPM SPMCSR SPMEN SPM * 6 - RWWSB:RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * 5 - Res: ATmega48/88/168 "0" * 4 - RWWSRE: RWW RWW() RWW(RWWSB"1") (SPMEN)RWW RWWSRE SPMEN"1" SPMRWW Flash (SPMEN ),RWW Flash RWWSRE Flash * 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P249" " * 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001" "01001" "00101" "00011" "00001"
244
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Flash
Z SPM
ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash (P261Table126 ) Figure118 Boot Loader Z Z SPM Boot Loader Z LPM Z Z LSB ( Z0) Figure 118. SPM(1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. Figure118 P252Table111
Flash
SPM 1 * * * * * 245
2
2545A-AVR-09/03
*
( ) Flash 1 Boot Loader - Flash 2 P251" Boot Loader "
246
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
SPM Z "X0000011" SPMCSR SPM R1 R0 Z PCPAGE Z * * ( ) RWW NRWW NRWW CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE SPM EEPROM
Z "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
SPM
SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P44" " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P44" " BLS RWW RWWSRE 1 RWWSB P251" Boot Loader "
BLS
RWW
247
2545A-AVR-09/03
SPM Boot Loader
Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader
R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Boot Loader Flash Table105 Table106 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7 6 1 0 "1" Flash EEPROM SPMCSR EEPROM Flash SPMCSR EECR EEWE 0x0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
0x0000ZSPMCSRBLBSET SPMEN SPMCSR CPU LPM (FLB) P256Table119
Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (FHB) P256Table120
Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
0x0002 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (EFB) P256Table118
Rd 7 - 6 - 5 - 4 - 3 EFB3 2 EFB2 1 EFB1 0 EFB0
"0" "1" Flash VCC CPU Flash Flash Flash
248
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Flash Flash CPU Flash ( ) 1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCSR Flash SPM Flash RC Flash Table108 CPU Flash Table 108. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
249
2545A-AVR-09/03
Boot Loader
;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi spmcrval, (1<; ;PAGESIZEB<=256
;PAGESIZEB<=256 subi
; execute Page Write subi ZL, low(PAGESIZEB) ; sbci ZH, high(PAGESIZEB) ;PAGESIZEB<=256 ldi spmcrval, (1<; ;PAGESIZEB<=256 ;
;PAGESIZEB<=256 subi
; RWW ; RWW Return: in temp1, SPMCSR sbrs temp1, RWWSB ; RWWSB "1" RWW ret ; RWW
250
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ldi spmcrval, (1<251
2545A-AVR-09/03
ATmega88 Boot Loader
Table109 Table111 Table 109. ATmega88 Boot (1)
Boot 128 256 512 1024 Boot Loader Flash 0xF80 0xFFF 0xF00 0xFFF 0xE00 0xFFF 0xC00 0xFFF Boot ( Boot Loader ) 0xF80 0xF00 0xE00 0xC00
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
4 8 16 32
Flash 0x000 0xF7F 0x000 0xEFF 0x000 0xDFF 0x000 0xBFF
0xF7F 0xEFF 0xDFF 0xBFF
Note:
BOOTSZ Figure117.
Table 110. ATmega88 RWW (1)
Flash - (RWW) - (NRWW) 96 32 0x000 - 0xBFF 0xC00 - 0xFFF
"
P242"NRWW - - " P241"RWW - -
Table 111. ATmega88 Figure118 Z (1)
PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: PC[11:5] PC[4:0] 11 4 Z12 Z5 Z12:Z6 Z5:Z1 Z ( 12 PC[11:0]) ( 32 5 PC [4:0]). Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z15:Z13 Z0 SPM "0" LPM Z P246" Flash"
252
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega168 Boot Loader Table112 Table114 Table 112. ATmega168 Boot (1)
Boot 128 256 512 1024 Boot Loader Flash 0x1F80 0x1FFF 0x1F00 0x1FFF 0x1E00 0x1FFF 0x1C00 0x1FFF Boot ( Boot Loader ) 0x1F80 0x1F00 0x1E00 0x1C00
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
4 8 16 32
Flash 0x0000 0x1F7F 0x0000 0x1EFF 0x0000 0x1DFF 0x0000 0x1BFF
0x1F7F 0x1EFF 0x1DFF 0x1BFF
Note:
BOOTSZ Figure117
Table 113. ATmega168 RWW (1)
Flash - (RWW) - (NRWW) 112 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF
- "
P242"NRWW - - " P241"RWW -
Table 114. ATmega168 Figure118 Z (1)
PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: PC[12:6] PC[5:0] 12 5 Z13 Z6 Z13:Z7 Z6:Z1 Z ( 12 PC[11:0]) ( 32 5 PC [4:0]). Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z15:Z14 Z0 SPM "0" LPM Z P246" Flash"
253
2545A-AVR-09/03
ATmega88/168 6 ("0") ("1") Table116 "1" ATmega48
Boot Loader SPMEN ("0")SPM Flash SPM
Table 115. (1)
7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
1. "1" "0"
Table 116. (1)(1)
LB 1 2 3 Notes: Notes: LB2 1 1 0 LB1 1 0 0 Flash EEPROM (1) Flash EEPROM (1)
1. LB1 LB2 Boot 1. "1" , "0"
254
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 117. ATmega88/168 (1)(1)
BLB0 1 2 BLB02 1 1 BLB01 1 0 SPM LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 BLB1 1 2
0 BLB12 1 1
1 BLB11 1 0
3
0
0
4 Notes:
0
1
1. LB1 LB2 Boot 2. "1" , "0"
255
2545A-AVR-09/03
ATmega48/88/168 Table118 - Table120 "0" Table 118. mega48
- - - - - - - SPMEN Notes: 7 6 5 4 3 2 1 0 - - - - - - - SPM 1 1 1 1 1 1 1 1 ( )
1. BODLEVEL P39Table21 2. RSTDISBL P69" C "
Table 119. mega88/168
- - - - - BOOTSZ1 BOOTSZ0 BOOTRST Note: 7 6 5 4 3 2 1 0 - - - - - Boot ( Table 113 ) Boot ( Table 113 ) 1 1 1 1 1 0 ( )(1) 0 ( )(1) 1 ( )
1. BOOTSZ1..0 Boot P259Table122
Table 120.
RSTDISBL DWEN SPIEN
(2) (1)
7 6 5 4 3 2 1 0
EEPROM
1 ( ) 1 ( ) 0 ( SPI ) 1 ( ) 1 ( )EEPROM 1 ( ) 1 ( ) 1 ( )
WDTON(3) EESAVE BODLEVEL2(4) BODLEVEL1 BODLEVEL0 Notes:
(4) (4)
BOD BOD BOD
1. RSTDISBL P69" C "
256
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
2. SPIEN 3. P44" - WDTCSR" 4. P39Table21 BODLEVEL
Table 121.
CKDIV8(4) CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Note:
(3)
7 6 5 4 3 2 1 0
8
0 ( ) 1 ( ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 1 ( )(2) 0 ( )(2)
1. SUT1..0 P28Table12 2. CKSEL3..0RC8 MHz P27Table11 3. CKOUT PORTB0 P31" " 4. P31" "
1(LB1) EESAVE
257
2545A-AVR-09/03
Atmel 1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x92 ( 4KB Flash ) 3. 0x002: 0x05 ( 0x001 0x92 ATmega48 )
ATmega48
ATmega88
1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x93 ( 8KB Flash ) 3. 0x002: 0x0A ( 0x001 0x93 ATmega88 )
ATmega168
1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x94 ( 16KB Flash ) 3. 0x002: 0x06 ( 0x001 0x94 ATmega168 )
ATmega48/88/168 RC 0x000 OSCCAL RC
258
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega48/88/168 Flash EEPROM 250 ns
ATmega48/88/168 Figure119 Table122 XA1/XA0 XTAL1 Table124 WR OE Table125 Figure 119.
+5V
RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2
PD1 PD2 PD3 PD4 PD5 PD6
VCC
+5V AVCC
PC[1:0]:PB[5:0]
DATA
PD7 RESET PC2
XTAL1 GND
Table 122.
RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC2 {PC[1:0]: PB[5:0]} I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE )
259
2545A-AVR-09/03
Table 123.
PAGEL XA1 XA0 BS1 Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
Table 124. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 )
260
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Table 125.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 126. Flash
ATmega48 ATmega88 ATmega168 Flash 2K (4K ) 4K (8K ) 8K (16K ) 32 32 64 PCWORD PC[4:0] PC[4:0] PC[5:0] 64 128 128 PCPAG E PC[10:5] PC[11:5] PC[12:6] PCMSB 10 11 12
Table 127. EEPROM
ATmega48 ATmega88 ATmega168 EEPROM 256 512 512 4 4 4 PCWORD EEA[1:0] EEA[1:0] EEA[1:0] 64 128 128 PCPAG E EEA[7:2] EEA[8:2] EEA[8:2] EEAMSB 7 8 8
Table 128.
MOSI MISO SCK PB3 PB4 PB5 I/O I O I t
261
2545A-AVR-09/03
1. VCC GND 4.5 - 5.5V 2. RESET XTAL1 6 3. P260Table123 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable 5. 50 s * * * 0xFF Flash EEPROM( EESAVE ) Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 10 2. BS1 0 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P261Table126 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 1. XA1 XA0 "00" 2. BS1 "0" 3. DATA (0x00 - 0xFF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF)
262
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure121 ) F. B E FLASH P264Figure 120 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA (0x00 - 0xFF) 4. XTAL1 H. 1. WR RDY/BSY 2. RDY/BSY ( Figure121 ) I. B H Flash J. 1. 1. XA1 XA0 "10" 2. DATA "0000 0000" XTAL1
263
2545A-AVR-09/03
Figure 120. Flash (1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P261Table126
Figure 121. Flash (1)
F
A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. "XX" Flash
EEPROM
P261Table127 EEPROM EEPROM EEPROM ( P263" Flash " ) 1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM
264
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
1. BS 0 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure122 ) Figure 122. EEPROM
K
A
DATA 0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P263" Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA Flash 5. BS "1" DATA Flash 6. OE "1"
EEPROM
( P263" Flash " ) 1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA EEPROM 5. OE "1"
265
2545A-AVR-09/03
( P263" Flash " ) 1. A "0100 0000" 2. C "0" 3. WR RDY/BSY
( P263" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0"
( P263" Flash " ) 1. 1. A "0100 0000" 2. 2. C "0" 3. 3. BS1 "1" BS2 "1" 4. 4. WR RDY/BSY 5. 5. BS2 "0" Figure 123.
Write Fuse Low byte A
DATA
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
( P263" Flash " ) 1. A "0010 0000" 2. C. n "0" LB 3(LB1 LB2 ) 3. WR RDY/BSY
( P263" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE"0" BS2BS1"1" DATA("0")
266
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
4. OE BS1 "0" BS2 "1" DATA ("0" ) 5. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 6. OE "1" Figure 124. BS1 BS2
Fuse Low Byte 0
0 Extended Fuse Byte BS2 Lock Bits 0 1 1 DATA
Fuse High Byte BS2
1
BS1
( P263" Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE "0" BS1 "1" DATA 4. OE "1"
( P263" Flash " ) 1. A "0000 1000" 2. B 0x00 3. OE "0" BS1 "1" DATA 4. OE "1"
Figure 125.
tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1, BS2) tBVPH PAGEL WR RDY/BSY tWLRH tPHPL tWLWH tPLWL
WLRL
tXHXL tXLDX
tPLBX t BVWL
tWLBX
267
2545A-AVR-09/03
Figure 126. (1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure125 (tDVXH tXHXL tXLDX)
Figure 127. ( )(1)
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure125 ( tDVXH tXHXL tXLDX)
Table 129. VCC = 5V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL 67 200 150 67 0 0 11.5 12.5 250 V A ns ns ns ns ns ns
268
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Table 129. VCC = 5V 10% (Continued)
tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2. PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE
(2)
150 67 150 67 67 67 67 150 0 3.7 7.5 0 0

ns ns ns ns ns ns ns ns
1 4.5 9
s ms ms ns
250 250 250
ns ns ns
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P261Table128 SPI SPI SPI Figure 128. (1)
+1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI MISO SCK XTAL1 AVCC
RESET
GND
Notes:
1. XTAL1 2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 1.8 - 5.5V
269
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EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU >
270
ATmega48/88/168
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ATmega48/88/168 SCK ATmega48/88/168 SCK Figure129 ATmega48/88/168 ( Table131 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash 6 LSB 8 tWD_FLASH ( Table130.) Flash 5. EEPROM EEPROM tWD_EEPROM ( Table130.) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC Flash Flash 0xFF Flash 0xFF 0xFF tWD_FLASH 0xFF 0xFF tWD_FLASH Table130 EEPROM 0xFF 0xFF 0xFF 0xFF EEPROM 0xFF tWD_EEPROM tWD_EEPROM Table130 Table 130. Flash EEPROM
tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 3.6 ms 9.0 ms
EEPROM
271
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Figure 129.
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
Table 131.
1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 000a aaaa 000x xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxbb bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b o i EEPROM EEPROM a:b EEPROM "0" "1" P254Table115 "0" P254Table115 b o "0" "1" Table XXX on page XXX "0" "1" P221Table98
EEPROM EEPROM EEPROM ( ) EEPROM( )
0100 1100 1010 0000 1100 0000 1100 0001
000a aaaa 000x xxaa 000x xxaa 0000 0000
bbxx xxxx bbbb bbbb bbbb bbbb 0000 00bb
xxxx xxxx oooo oooo iiii iiii iiii iiii
1100 0010 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 1010 1100 0101 0000
00xx xxaa 0000 0000 111x xxxx 000x xxxx 1010 0000 1010 1000 1010 0100 0000 0000
bbbb bb00 xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii xxxx xxii oooo oooo
P256Table118
"0" "1"
Read Fuse bits. "0" = programmed, "1" = unprogrammed. See "0" "1" Table XXX on page XXX
272
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Table 131. (Continued)
RDY/BSY Note: 1 0101 1000 0101 0000 0011 1000 1111 0000 2 0000 1000 0000 1000 000x xxxx 0000 0000 3 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 4 oooo oooo oooo oooo oooo oooo xxxx xxxo "0" "1" P221Table98 "0" "1" P256Table118 o = "1" "0"
a = b = H = 0 - 1 - o = i = x =
SPI
SPI P280 "SPI "
273
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*
........................................................ -55C +125C ........................................................ -65C +150C RESET............ -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " "
VCC GND ................................ 200.0 mA
VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH VOH1 IIL IIH RRST RPU
TA = -40C-85C, VCC = 1.8V-5.5V ( )
XTAL1 RESET XTAL1 RESET XTAL1 RESET XTAL1 RESET (3) PC6 (3)PC6 Output High Voltage(4), Except PC6 (4) PC6 I/O I/O Reset I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 5.5V VCC = 1.8V - 5.5V VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 5.5V IOL = 10mA, VCC = 5V IOL = 5mA, VCC = 3V TBD IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V TBD VCC = 5.5V, pin low (absolute value) VCC = 5.5V, pin high (absolute value) 30 20 4.2 2.3 TBD 1 1 60 50 -0.5 -0.5 -0.5 -0.5 0.7VCC(2) 0.6VCC(2) 0.8VCC(2) 0.7VCC(2) 0.9VCC(2) 0.2VCC(1) 0.3VCC(1) 0.1VCC(1) 0.1VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5 TBD V V V V V V V V V V A A k k
274
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TA = -40C-85C, VCC = 1.8V-5.5V ( ) (Continued)
1MHzVCC = 2V (ATmega48/88/168V) 4MHzVCC = 3V (ATmega48/88/168L) 8MHzVCC = 5V (ATmega48/88/168) 1MHz VCC = 2V (ATmega48/88/168V) 4MHzVCC = 3V (ATmega48/88/168L) 8MHzVCC = 5V (ATmega48/88/168) VACIO IACLK tACID Notes: WDT VCC = 3V WDT VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 <8 <1 <10 0.25 0.55 3.5 12 0.5 1.5 5.5 15 2 40 50 mA mA mA mA mA mA A A mV nA ns
ICC
1. " " 2. " " 3. ()I/O(20 mA CC = 5V10 mAVCC = 3V) V ATmega48 1] C0 - C5 IOL 70 mA 2] C6 D0 - D4 IOL 70 mA 3] B0 - B7 D5 - D7 IOL 70 mA ATmega88/168 1] C0 - C5 IOL 100 mA 2] C6D0 - D4 IOL 100 mA 3] B0 - B7 D5 - D7 IOL 100 mA IOL VOL 4. ( ) I/O (20 mA CC = 5V 10 mAVCC = 3V) V ATmega48 1] C0 - C5 IOH 70 mA 2] C6 D0 - D4 IOH 70 mA 3] B0 - B7 D5 - D7 IOH 70 mA. ATmega88/168 1] C0 - C5 IOH 100 mA 2] C6D0 - D4 IOH 100 mA 3] B0 - B7 D5 - D7 IOH 100 mA. IOH VOH 5. AVR
275
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Figure 130.
V IH1 V IL1
Table 132.
VCC=1.8-5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 500 200 200 2.0 2.0 2 2 VCC=2.7-5.5V 0 125 50 50 1.6 1.6 2 8 VCC=4.5-5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
Note:
AVR
Figure 131. ATmega48V/88V/168V VCC
10 MHz
Safe Operating Area
4 MHz
1.8V
2.7V
5.5V
276
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ATmega48/88/168
Figure 132. ATmega48/88/168 VCC
20 MHz
10 MHz
Safe Operating Area
2.7V
4.5V
5.5V
277
2545A-AVR-09/03
Table133 ATmega48/88/168 Figure133 Table 133.
VIL VIH Vhys tr(1) tof(1) tSP(1) Ii Ci(1) fSCL
(1)
SDA SCL VIHmin VILmax I/O I/O SCL fCK(4)
-0.5 0.7 VCC 0.05 VCC
(2)
0.3 VCC VCC + 0.5 - 0.4 300 250 50
(2)
V V V V ns ns ns A pF kHz s s s s s s s s s s ns ns s s s s
VOL(1)
3 mA
(3)
0 20 + 0.1Cb(3)(2)
10 pF < Cb < 400 pF
20 + 0.1Cb 0 -10 -
(3)(2)
0.1VCC < Vi < 0.9VCC > max(16fSCL, 250kHz) fSCL 100 kHz
(5)
10 10 400 1000ns -----------------Cb 300ns --------------Cb - - - - - - - - 3.45 0.9 - - - - - -
0 V CC - 0,4V ----------------------------3mA V CC - 0,4V ----------------------------3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 1.3
Rp
fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz
(6) (7)
tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Notes: 1. 2. 3. 4.
(repeated) START SCL SCL repeated START STOP STOP START
fSCL > 100 kHz
fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz
ATmega48/88/168 100% fSCL > 100 kHz Cb pF fCK CPU
278
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ATmega48/88/168
5. ATmega48/88/168 fSCL 6. ATmega48/88/168 (1/fSCL - 2/fCK) fSCL = 100 kHz fCK 6 MHz 7. ATmega48/88/168 (1/fSCL - 2/fCK) fCK = 8 MHz fSCL > 308 kHz ATmega48/88/168 (400 kHz) tLOW
Figure 133.
tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tr
tBUF
SPI
Figure134 Figure135 Table 134. SPI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK SCK SCK SCK SCK SS SCK SCK (1) SCK SCK SS SS 20 10 10 tck 15 4 * tck 2 * tck 1600 Table71 50% 3.6 10 10 0.5 * tsck 10 10 15 ns
SS SCK 20 1. SPI SCK fCK < 12 MHz - 2 tCLCL fCK > 12 MHz - 3 tCLCL 2. AVR
279
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Figure 134. SPI ( )
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 135. SPI ( )
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
280
ATmega48/88/168
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ATmega48/88/168
ADC --
Table 135. ADC
VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 1 MHz ( INL DNL ) VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 1 MHz (INL) (DNL) AVCC VREF VIN VINT RREF RAIN Note: 1.0 VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz 13 50 VCC - 0.3 1.0 GND 38.5 1.1 32 100 1.2 10 2 4.5 2.5 Bits LSB LSB
2
LSB
4.5
LSB
0.5 0.25 2 2 260 1000 VCC + 0.3 AVCC VREF
LSB LSB LSB LSB s kHz V V V kHz V k M
AVR
281
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ATmega48/88/168 -
AVR
I/O I/O I/O I/O CL*VCC*f CL = VCC = f = I/O Figure 136. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
1.2
1
5.5 V 5.0 V
0.8
4.5 V 4.0 V 3.3 V
ICC (mA)
0.6
0.4
2.7 V 1.8 V
0.2
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
282
ATmega48/88/168
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ATmega48/88/168
Figure 137. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 24 MHz
18 16 14 12
5.5V 5.0V 4.5V
ICC (mA)
10 8 6
4.0V 3.3V
4 2 0 0 4 8
2.7V 1.8V
12 16 20 24
Frequency (MHz)
Figure 138. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
7 6 5
25 C -40 C 85 C
ICC (mA)
4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
283
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Figure 139. VCC ( RC CKDIV8 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
1.4 1.2 1
25 C -40 C 85 C
ICC (mA)
0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 140. VCC (32 kHz )
ACTIVE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR
60
50
25 C
40
ICC (uA)
30
20
10
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
284
ATmega48/88/168
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ATmega48/88/168
Figure 141. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
0.18 0.16 0.14 0.12
5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V
ICC (mA)
0.1 0.08 0.06 0.04 0.02
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
Figure 142. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 24 MHz
4.5
4
3.5
5.5V 5.0V 4.5V 4.0V
3
ICC (mA)
2.5
2
1.5
3.3V 2.7V 1.8V
0 4 8 12 16 20 24
1
0.5 0
Frequency (MHz)
285
2545A-AVR-09/03
Figure 143. VCC ( RC 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
1.6 1.4 1.2 1
85 C 25 C -40 C
ICC (mA)
0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 144. VCC ( RC CKDIV8 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
0.35 0.3 0.25
85 C 25 C -40 C
ICC (mA)
0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
286
ATmega48/88/168
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ATmega48/88/168
Figure 145. VCC (32 kHz )
IDLE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR
30
25
25 C
20
ICC (uA)
15
10
5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 146. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
2.5
85 C
2
ICC (uA)
1.5
1
25 C -40 C
0.5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
287
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Figure 147. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
12
10
8
85 C -40 C 25 C
ICC (uA)
6
4
2
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 148. VCC ( )
POWER-SAVE SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
12
10
25 C
8
ICC (uA)
6
4
2
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
288
ATmega48/88/168
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ATmega48/88/168
Standby Figure 149. Standby VCC
STANDBY SUPPLY CURRENT vs. VCC
Low Power Crystal Oscillator
180 160 140 120 4 MHz Res. 4 MHz Xtal 2 MHz Xtal 2 MHz Res. 455kHz Res. 1 MHz Res. 6 MHz Xtal 6 MHz Res.
ICC (uA)
100 80 60 40 20
32 kHz Xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 150. Standby VCC
STANDBY SUPPLY CURRENT vs. VCC
Full Swing Crystal Oscillator
500 450 400 350
ICC (uA)
16 MHz Xtal
12 MHz Xtal
300 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 MHz Xtal (ckopt) 4 MHz Xtal (ckopt) 2 MHz Xtal (ckopt)
VCC (V)
289
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Figure 151. I/O (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 5V
160 140 120
85 C
25 C -40 C
100
IOP (uA)
80 60 40 20 0 0 1 2 3
VOP (V)
4
5
6
Figure 152. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7V
90 80
85 C
70 60
25 C -40 C
IOP (uA)
50 40 30 20 10 0 0 0.5 1 1.5
VOP (V)
2
2.5
3
290
ATmega48/88/168
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Figure 153. (Reset) Reset (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
120
-40C
100
25C 85C
80
IRESET (uA)
60
40
20
0 0 1 2 3 4 5 6
VRESET (V)
Figure 154. (Reset) Reset (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V 70 60
-40 C
50
IRESET (uA)
25 C 85 C
40 30 20 10 0 0 0.5 1 1.5 VRESET (V) 2 2.5 3
291
2545A-AVR-09/03
Figure 155. I/O B PC5..0 D (VCC= 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
90 80 70 60
-40 C 25 C 85 C
IOH (mA)
50 40 30 20 10 0 0 1 2 3
VOH (V)
4
5
6
Figure 156. I/O B PC5..0 D (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
35 30 25 20 15 10 5 0 0 0.5 1 1.5
VOH (V)
-40 C 25 C 85 C
IOH (mA)
2
2.5
3
292
ATmega48/88/168
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Figure 157. B PC5..0 D (VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
25 C -40 C
8 7 6
9
85 C
IOH (mA)
5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1
VOH (V)
1.2
1.4
1.6
1.8
2
Figure 158. I/O B PC5..0 D (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
80
25 C
70 60 50
85 C
IOL (mA)
40 30 20 10 0 0 0.5 1 1.5 2 2.5
VOL (V)
293
2545A-AVR-09/03
Figure 159. I/O B PC5..0 D (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
40 35 30 25
-40 C 25 C 85 C
IOL (mA)
20 15 10 5 0 0 0.5 1 1.5 2 2.5
VOL (V)
Figure 160. I/O B PC5..0 D (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-40 C 25 C 85 C
IOL (mA)
VOL (V)
294
ATmega48/88/168
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Figure 161. I/O VCC (VIH, I/O "1")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
2.5
25 C 85 C -40 C
2
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 162. I/O VCC (VIL, I/O "0")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
3
2.5
85 C -40 C 25 C
2
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
295
2545A-AVR-09/03
Figure 163. Reset VCC (VIH,Reset "1")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
2.5
25 C 85 C -40 C
2
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 164. Reset VCC (VIL,Reset "0")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
3
2.5
2
-40 C 85 C 25 C
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
296
ATmega48/88/168
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ATmega48/88/168
Figure 165. Reset VCC
RESET PIN INPUT HYSTERESIS vs. VCC
600
500
Input Hysteresis (mV)
400
VIL
300
200
100
0 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
BOD
Figure 166. BOD (BOD 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.0V
4.5
4.45
Rising Vcc
4.4
Threshold (V)
4.35
4.3
Falling Vcc
4.25
4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
297
2545A-AVR-09/03
Figure 167. BOD (BOD 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V
2.9
2.85
Rising Vcc
2.8
Threshold (V)
2.75
2.7
Falling Vcc
2.65
2.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Figure 168. BOD (BOD 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 1.8V
1.86
1.84
Rising Vcc
Threshold (V)
1.82
1.8
Falling Vcc
1.78
1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
298
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 169. VCC
BANDGAP VOLTAGE vs. V CC
1.1
Bandgap Voltage (V)
1.095
-40 C
1.09
85 C
1.085
1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VCC (V)
Figure 170. (VCC = 5V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC =5V
0.009
Analog comparator offset voltage (V)
0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
85 C -40 C
Common Mode Voltage (V)
299
2545A-AVR-09/03
Figure 171. (VCC = 2.7V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC=2.7V
4 3.5 Analog comparator offset voltage 3 2.5 (mV) 2
85 C -40 C
1.5 1 0.5 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5
Figure 172. BOD VCC
BROWNOUT DETECTOR CURRENT vs. VCC
32 30 28 26 24 22 20 18 1.5 2 2.5 3 3.5 4 4.5 5 5.5
-40 C
ICC (uA)
25 C 85 C
VCC (V)
300
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 173. ADC VCC (AREF = AVCC)
AREF vs. VCC
ADC AT 50 KHz
500 450 400 350 300 250 200 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5
-40 C 25 C 85 C
ICC (uA)
VCC (V)
Figure 174. AREF VCC
AREF vs. VCC
ADC AT 1 MHz
180 160 140 120
85 C 25 C -40 C
ICC (uA)
100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
301
2545A-AVR-09/03
Figure 175. VCC
ANALOG COMPARATOR CURRENT vs. VCC
140
-40 C
120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
25 C 85 C
ICC (uA)
VCC (V)
Figure 176. VCC
ANALOG COMPARATOR CURRENT vs. VCC
140
-40 C
120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
25 C 85 C
ICC (uA)
VCC (V)
302
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
Figure 177. Programming Current vs. VCC
PROGRAMMING CURRENT vs. Vcc
14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5
-40 C
25 C 85 C
ICC (mA)
VCC (V)
Figure 178. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. VCC
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
0.18
5.5 V
0.16
5.0 V
0.14
4.5 V
0.12
ICC (mA)
4.0 V
0.1 0.08 0.06 0.04 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
3.3 V 2.7 V 1.8 V
Frequency (MHz)
303
2545A-AVR-09/03
Figure 179. VCC (1 - 20 MHz )
RESET SUPPLY CURRENT vs. VCC
1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
4.5 4 3.5 3
5.5V 5.0V 4.5V
ICC (mA)
2.5 2 1.5
4.0V 3.3V
1
2.7V
0.5
1.8V
0 0 4 8 12 16 20 24
Frequency (MHz)
Figure 180. VCC
RESET PULSE WIDTH vs. VCC
2500
2000
Pulsewidth (ns)
1500
1000
500
85 C -40 C 25 C
0 1.5 2 2.5 3 3.5
VCC (V)
4
4.5
5
5.5
304
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0)
UDR0 UBRR0H UBRR0L UCSR0C UCSR0B UCSR0A
7
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
USART I/O r USART USART - UMSEL01 RXCIE0 RXC0 - UMSEL00 TXCIE0 TXC0 - UPM01 UDRIE0 UDRE0 - UPM00 RXEN0 FE0 - USBS0 TXEN0 DOR0 -
UCSZ01 /UDORD0
168 172 172 -
UCSZ00 / UCPHA0
- UCPOL0 TXB80 MPCM0 171/182 170 169
UCSZ02 UPE0
RXB80 U2X0
305
2545A-AVR-09/03
(0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E)
TWAMR TWCR TWDR TWAR TWSR TWBR ASSR OCR2B OCR2A TCNT2 TCCR2B TCCR2A OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L TCCR1C TCCR1B TCCR1A DIDR1 DIDR0
7
- - TWAM6 TWINT TWA6 TWS7 - - -
6
- - TWAM5 TWEA TWA5 TWS6
5
- - TWAM4 TWSTA TWA4 TWS5 -
4
- - TWAM3 TWSTO TWA3 TWS4 - TCN2UB -
3
- - TWAM2 TWWC TWA2 TWS3 - OCR2AUB -
2
- - TWAM1 TWEN TWA1 - - OCR2BUB -
1
- - TWAM0 - TWA0 TWPS1 - TCR2AUB -
0
- - - TWIE TWGCE TWPS0 - TCR2BUB -
195 192 194 194 194 192 139 138 138 138 137 134
EXCLK - AS2 -
/ 2 B / 2 r A / 2(8 ) FOC2A COM2A1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FOC2B COM2A0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COM2B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COM2B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WGM22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS21 WGM21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS20 WGM20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
/ 1 B / 1 B / 1 A / 1 A / 1 / 1 / 1 / 1 - FOC1A ICNC1 COM1A1 - - - FOC1B ICES1 COM1A0 - - - - - COM1B1 - ADC5D - - WGM13 COM1B0 - ADC4D - - WGM12 - - ADC3D - - CS12 - - ADC2D - - CS11 WGM11 AIN1D ADC1D - - CS10 WGM10 AIN0D ADC0D
121 121 121 121 122 122 120 120 120 119 117 216 231
306
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
(0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C)
ADMUX ADCSRB ADCSRA ADCH ADCL TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 EICRA PCICR OSCCAL PRR CLKPR WDTCSR SREG SPH SPL SPMCSR MCUCR MCUSR SMCR MONDR ACSR SPDR SPSR SPCR GPIOR2 GPIOR1 OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR
7
- REFS1 - ADEN
6
- REFS0 ACME ADSC
5
- ADLAR - ADATE
4
- - - ADIF
3
- MUX3 - ADIE
2
- MUX2 ADTS2 ADPS2
1
- MUX1 ADTS1 ADPS1
0
- MUX0 ADTS0 ADPS0
227 231 228 229 229
ADC ADC - - - - - - - - - - PCINT23 - PCINT7 - - - - - PRTW1 - - CLKPCE WDIF I - SP7 - - - - - SPMIE - - - - - ACD - SPIF SPIE - - - - - - - - - - PCINT22 PCINT14 PCINT6 - - - - - PRTIM2 - - - WDIE T - SP6 - - - - - (RWWSB)5. - - - - - ACBG - WCOL SPE - - - - - - - - ICIE1 - PCINT21 PCINT13 PCINT5 - - - - - PRTIM0 - - - WDP3 H - SP5 - - - - - - - - - - - ACO - - DORD - - - - - - - - - - PCINT20 PCINT12 PCINT4 - - - - r - - - - - WDCE S - SP4 - - - - - (RWWSRE)5. - PUD - - - ACI - - MSTR - PRTIM1 - - CLKPS3 WDE V - SP3 - - - - - BLBSET - - WDRF SM2 - ACIE - SPI - CPOL I/O 2 I/O 1 - - - - - - - - / 0 B / 0 A / 0(8 ) FOC0A COM0A1 TSM FOC0B COM0A0 - - COM0B1 - - COM0B0 - WGM02 - - CS02 - - CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC - CPHA - SPR1 SPI2X SPR0 ACIC - ACIS1 - ACIS0 - - PRSPI - - CLKPS2 WDP2 N (SP10) 5. SP2 - - - - - PGWRT - - BORF SM1 - - PRUSART0 - - CLKPS1 WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF SM0 - - PRADC - - CLKPS0 WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE - - - - - - - - - - - PCINT19 PCINT11 PCINT3 - ISC11 - - - - - - - - - OCIE2B OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 - ISC10 PCIE2 - - - - - - - - OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 - ISC01 PCIE1 - - - - - - - - TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 - ISC00 PCIE0 -
140 122 93 79 79 79 76
29
31 44 8 10 10
244
33
214 150 150 148 22 22
96/142 17 17 17
(EEPROM ) 5. EEPROM EEPROM - - - - - - EEPM1 - - EEPM0 - - EERIE - - EEMPE - - EEPE INT1 INTF1 EERE INT0 INTF0 I/O 0
17 22 77 77
307
2545A-AVR-09/03
0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x0 (0x20)
PCIFR TIFR2 TIFR1 TIFR0 PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB
7
- - - - - - - - - - - - - - - - PORTD7 DDD7 PIND7 - - - PORTB7 DDB7 PINB7 - - -
6
- - - - - - - - - - - - - - - - PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 - - -
5
- - - - - ICF1 - - - - - - - - - - PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 - - -
4
- - - - - - - - - - - - - - - - PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 - - -
3
- - - - - - - - - - - - - - - - PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 - - -
2
PCIF2 - - - OCF2B OCF1B OCF0B - - - - - - - - - PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 - - -
1
PCIF1 - - - OCF2A OCF1A OCF0A - - - - - - - - - PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 - - -
0
PCIF0 - - - TOV2 TOV1 TOV0 - - - - - - - - - PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 - - -
141 123
75 75 75 75 75 75 75 75 75
Note:
1. "0" I/O 2. SBI CBI 0x00 - 0x1F I/O SBIS SBIC 3. "1" AVR CBI SBI CBI SBI 0x00 - 0x1F 4. I/OINOUT 0x00 - 0x3FI/O LD ST I/O 0x20 ATmega48/88/168 64 IN OUT SRAM 0x60 - 0xFF I/O ST/STS/STD LD/LDS/LDD 5. ATmega88/168
308
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168

1 2

#
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
RJMP IJMP JMP(1) RCALL ICALL CALL(1) RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS
k k k k
(Z) (Z)
None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None
2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k
"0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1"
309
2545A-AVR-09/03
BRVC BRIE BRID k k k
"0"
if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1
None None None
#
1/2 1/2 1/2
SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b I/O I/O T T 2 2 SREG T SREG T SREG SREG I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN Rd, P Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr SRAM SRAM I/O Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1
310
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
OUT PUSH POP Rr Rd
P, Rr I/O
P Rr STACK Rr Rd STACK
None None None
#
1 2 2
MCU
NOP SLEEP WDR BREAK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None None 1 1 1 N/A
Note:
1. ATmega168
311
2545A-AVR-09/03
ATmega48
(MHz) ATmega48V-2AI ATmega48V-2PI ATmega48V-2MI ATmega48V-2AJ(2) ATmega48V-2PJ(2) ATmega48V-2MJ(2) ATmega48-16AI ATmega48-16PI ATmega48-16MI ATmega48-16AJ(2) ATmega48-16PJ(2) ATmega48-16MJ(2) 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A
2(3)
1.8 - 5.5
(-40C 85C)
16(3)
2.7 - 5.5
(-40C 85C)
Note:
1. wafer Atmel 2. 3. P276Figure 131 P277Figure 132
32A 28P3 32M1-A 32- (1.0 mm) (TQFP) 28- 0.300" Plastic Dual Inline Package (PDIP) 32- 5 x 5 x 1.0mm 0.50 mm (MLF)
312
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega88
(MHz) ATmega88V-2AI ATmega88V-2PI ATmega88V-2MI ATmega88V-2AJ(2) ATmega88V-2PJ(2) ATmega88V-2MJ(2) ATmega88-16AI ATmega88-16PI ATmega88-16MI ATmega88-16AJ(2) ATmega88-16PJ(2) ATmega88-16MJ(2) 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A
2(3)
1.8 - 5.5
(-40C 85C)
16(3)
2.7 - 5.5
(-40C 85C)
Note:
1. wafer Atmel 2. 3. P276Figure 131 P277Figure 132
32A 28P3 32M1-A 32- (1.0 mm) (TQFP) 28- 0.300" Plastic Dual Inline Package (PDIP) 32- 5 x 5 x 1.0mm 0.50 mm (MLF)
313
2545A-AVR-09/03
ATmega168
(MHz) ATmega168V-2AI ATmega168V-2PI ATmega168V-2MI ATmega168V-2AJ(2) ATmega168V-2PJ(2) ATmega168V-2MJ(2) ATmega168-16AI ATmega168-16PI ATmega168-16MI ATmega168-16AJ(2) ATmega168-16PJ(2) ATmega168-16MJ(2) 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A
2(3)
1.8 - 5.5
(-40C 85C)
16(3)
2.7 - 5.5
(-40C 85C)
Note:
1. wafer Atmel 2. 3. P276Figure 131 P277Figure 132
32A 28P3 32M1-A 32- (1.0 mm) (TQFP) 28- 0.300" Plastic Dual Inline Package (PDIP) 32- 5 x 5 x 1.0mm 0.50 mm (MLF)
314
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
32A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
315
2545A-AVR-09/03
28P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
B2
A1
(4 PLACES)
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 - NOM - - - - - - - - - - - MAX 4.5724 - 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 B2 L C eB e
2.540 TYP
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B
R
316
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1 A
0.08 C
P D2
Pin 1 ID
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75BSC 2.95 3.10 0.50 BSC 0.30 - - 0.40 - - 0.50 0.60 12o 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTE
1 2 3
P
A A1 E2 A2 A3 b D D1
b
e
L
D2 E
BOTTOM VIEW
E1 E2 e L
Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
P
0
01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. C
R
317
2545A-AVR-09/03
ATmega48 Rev A
ATmega48 * 1. 2.7 V EEPROM 0x00 0xFF 0xFF
318
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
ATmega88 Rev A
ATmega88 * 1. 2.7 V EEPROM 0x00 0xFF 0xFF
319
2545A-AVR-09/03
ATmega168 Rev A
ATmega168 * 1. 2.7 V EEPROM 0x00 0xFF 0xFF
320
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
........................................................................................................ 1 ................................................................................................ 2 ........................................................................................................ 3
................................................................................................................... ATmega48 ATmega88 ATmega168 .......................................... Disclaimer ............................................................................................................. ............................................................................................................... 3 4 5 5
................................................................................................ 6
AVR CPU ...................................................................................... 7
....................................................................................................................... 7 ............................................................................................................... 7 ALU - .................................................................................................... 8 ............................................................................................................ 9 ................................................................................................... 10 ............................................................................................................. 11 ...................................................................................................... 12 ................................................................................................... 12
AVR ATmega48/88/168 ....................................................... 15
Flash .................................................................. SRAM .............................................................................................. EEPROM ......................................................................................... I/O ........................................................................................................... 15 17 19 25
............................................................................ 26
............................................................................................... ................................................................................................................. ............................................................................................... ............................................................................................... ................................................................................................... RC ........................................................................................ 128 kHz ............................................................................................ ............................................................................................................. ................................................................................................... / ......................................................................................... ............................................................................................... 26 27 29 30 32 32 33 34 35 35 35
............................................................................ 38
............................................................................................................. ADC .............................................................................................. ............................................................................................................. ............................................................................................................. 39 39 39 39 i
2545A-AVR-09/03
Standby ...................................................................................................... 40 ................................................................................................... 40
.................................................................................... 42
...................................................................................................... 48 ...................................................................................................... 49 ............................................................... 53
...................................................................................................... 54
ATmega48 ....................................................................................... 55 ATmega88 ....................................................................................... 57 ATmega168 ..................................................................................... 60
I/O ................................................................................................ 65
..................................................................................................................... I/O ..................................................................................... ................................................................................................... I/O ......................................................................................... 65 66 70 82
.............................................................................................. 83 PWM 8 / 0 ............................................. 88
..................................................................................................................... / ..................................................................................... .......................................................................................................... ...................................................................................................... ............................................................................................... ............................................................................................................. / ..................................................................................... 8 / ....................................................................... 88 89 89 90 92 93 97 99
/ 0 / 1 ............................ 105
16 / 1 ...................................................................... 107
................................................................................................................... 16 ........................................................................................... / ................................................................................... ........................................................................................................ .................................................................................................... .................................................................................................... ............................................................................................. ........................................................................................................... / ................................................................................... 16 / ................................................................... 107 110 113 113 114 116 118 119 127 129
8-bit Timer/Counter2 with PWM and Asynchronous Operation .. 136
ii
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
................................................................................................................... / ....................................................................................... ........................................................................................................ .................................................................................................... ............................................................................................. ........................................................................................................... / ................................................................................... 8 / ..................................................................... / ............................................................................... / ............................................................................... 136 137 137 138 140 141 145 147 152 156
- SPI ........................................................................... 157
SS .................................................................................................. 162 ........................................................................................................... 165
USART0 ............................................................................................ 166
................................................................................................................... ........................................................................................................ ........................................................................................................ USART .................................................................................................. - USART ............................................................................... - USART ............................................................................... .................................................................................................... ............................................................................................. USART ....................................................................................... ............................................................................................. 166 167 170 171 173 176 179 183 184 189
SPI USART ................................................................ 193
................................................................................................................... ........................................................................................................ SPI .......................................................................................... ........................................................................................................ ........................................................................................................ USART MSPIM .......................................................................... AVR USART MSPIM AVR SPI............................................................................................................ 193 193 194 194 196 199 201
2 ...................................................................................... 203
................................................................................................................... 2 ...................................................................................... .................................................................................. ........................................................................... TWI .................................................................................................... TWI ............................................................................................. TWI ........................................................................................................... .................................................................................................... 203 203 204 207 209 211 215 218
iii
2545A-AVR-09/03
............................................................................................. 231
......................................................................................... 233
...................................................................................... 235
AD .......................................................................................... 236
................................................................................................................... ........................................................................................................... ......................................................................................... ................................................................................................. ADC ................................................................................................... ADC ................................................................................................... 236 238 239 242 243 247
debugWIRE ............................................................. 252
................................................................................................................... ................................................................................................................... ........................................................................................................... Software Break Points ....................................................................... debugWIRE ........................................................................................... debugWIRE ................................................................................ 252 252 252 253 253 253
ATmega48 Flash ............................................................... 254
Flash ...................................................................................... 255
Boot Loader - Read-While-Write , ATmega88 ATmega168....................................................................................... 261
Boot Loader .............................................................................................. Boot Loader .................................................................................. Read-While-Write Read-While-Write Flash ......................................... Boot Loader .......................................................................................... Boot Loader .............................................................................................. Flash ...................................................................................... Flash .................................................................................................. 261 261 261 264 265 267 268
..................................................................................... 276
.................................................................................. ............................................................................................................... ............................................................................................................... ........................................................................................................... ....................................................................... ................................................................................................. P ........................................................................................................ ........................................................................................................... 276 278 280 280 281 283 284 292
iv
ATmega48/88/168
2545A-AVR-09/03
ATmega48/88/168
............................................................................................ 296
*............................................................................................................. DC ............................................................................................................ ............................................................................................. .................................................................................................... 2 .............................................................................................. SPI ..................................................................................................... ADC - ........................................................................................ 296 296 298 298 300 301 303
ATmega48/88/168 - ........................................... 304
......................................................................................... 332 ......................................................................................... 336 ............................................................................................ 339
ATmega48 ........................................................................................................ 339 ATmega88 ........................................................................................................ 340 ATmega168 ...................................................................................................... 341
............................................................................................ 342
32A ................................................................................................................... 342 28P3 ................................................................................................................. 343 32M1-A ............................................................................................................. 344
ATmega48 ................................................................................. 345
Rev A ................................................................................................................ 345
ATmega88 ................................................................................. 346
Rev A ................................................................................................................ 346
ATmega168 ............................................................................... 347
Rev A ................................................................................................................ 347
..................................................................................................... i
v
2545A-AVR-09/03
vi
ATmega48/88/168
2545A-AVR-09/03
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
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Literature Requests
www.atmel.com/literature
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2545A-AVR-09/03

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